Intel Corporation

Yoni Aizik

Efraim Rotem

Eliezer Weissmann

Doron Rajwan

Nir Rosenzweig

Hisham Abu Salah

Yevgeni Sabin

Nadav Shulman

Esfir Natanzon

Arik Gihon

Ido Melamed

Chen Ranel

Paul S Diefenbaugh

Alexander Gendler

Michael Mishaeli

Gal Leibovich

Daniel D Lederman

Barnes Cooper

Guy M Therien

Tomer Ziv

Niv Tokman

Shay Levy

Eric C Samson

Gila Kamhi

Ahmad Yasin

Tsvika Kurts

Kevin Safford

Robert P Adler

Larisa Novakovsky

Shaun M Conrad

Hisham Shafi

Tal Kuzi

Hermann Gartler

Amit Moran

Itai Feit

Christopher J Lake

Nimrod Angel

Hem Doshi

Michael J St Clair

Ki W Yoon

Yoav Ben-Raphael

William Penner

Bart Plackle

Ben Furman

Natanel Abitan

Edward Vaiberman

Robert Hesse

Limor David

Eliezer Weissman

Reena Patel

Vijay Degalahal

A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.

System, apparatus and method for loose lock-step redundancy power management

Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.

Application priority based power management for a computer device

Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Device, method and system for transparently changing a frequency of an interconnect fabric

In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.

System, apparatus and method for responsive autonomous hardware performance state control of a processor

Embodiments include an autonomous core perimeter, configured to save the state of a core of a multi-core processor prior to the processor package being placed into a low-power state. The autonomous core perimeter of each core is configured to save an image of a microcontroller firmware to an external store if it has not been previously saved by another core, along with the unique working state information of that core's microcontroller. Upon restore, the single microcontroller firmware image is retrieved from the external store and pushed to each core along with each core's unique working state.

Autonomous core perimeter for low power processor states

System, apparatus and method for loose lock-step redundancy power management in a processor

In one embodiment, an apparatus includes a bulk write circuit to generate a bulk write message to send to a destination agent to cause the destination agent to write data comprising register contents into a plurality of registers, at least some of the plurality of registers comprising non-consecutive registers. The bulk write message may include a first message header, a first chunk header including an address of a first register of a first subset of the plurality of registers, and a first payload portion having the register contents for the first subset of the plurality of registers. Other embodiments are described and claimed.

System, apparatus and method for bulk register accesses in a processor

Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.

Supporting hang detection and data recovery in microprocessor systems

Growing community of inventors

Haifa, Israel

Yoni Aizik