Intel Corporation

Yongzhi Zhang

Kent D Glossop

Simon C Steely, Jr

Kermin Elliott Fleming, Jr

Dennis Ryan Bradford

Fabrizio Petrini

Mitchell Diamond

Benjamin Keen

Barry Tannenbaum

Uma Srinivasan

Jim Sukha

Systems, methods, and apparatuses relating to operations in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value.

Apparatuses, methods, and systems for operations in a configurable spatial accelerator

Embodiments are directed to techniques to determine dataflow graph instructions comprising one or more pick/switch instruction pairs and generate a reverse static single assignment graph based on the dataflow graph instructions, the reverse static single assignment graph comprising strongly connected components, each of the strongly connected components associated with at least one of the one or more pick/switch instruction pairs. Embodiments also include traversing the reverse static single assignment graph depth-first, and replace pick/switch instructions associated with strongly connected components having configuration values with compound instructions.

Sequence optimizations in a high-performance computing environment

Methods and apparatus to convert a non-series-parallel control flow graph to data flow. An example apparatus includes a node analyzer to detect a non-series-parallel node in sequential code, and an instruction generator to: generate instructions for prior nodes associated with the detected non-series-parallel node including a consumption operand, generate a combination instruction to combine results of the instructions generated for the prior nodes, and output the combination instructions and the instructions generated for the prior nodes to generate data flow code.

Methods and apparatus to convert a non-series-parallel control flow graph to data flow

Methods, apparatus, systems and articles of manufacture to compiler compile code to generate dataflow code are described. An example compiler apparatus includes an intermediate representation transformer to transform input software code to intermediate representation code; an instruction selector to insert machine instructions of a target execution platform in the intermediate representation code to generate machine intermediate representation code; and a target machine transformer to: convert a portion of the machine intermediate representation code to dataflow code to generate dataflow intermediate representation code; and allocate registers within the dataflow intermediate representation code.

Methods and apparatus to compile code to generate data flow code

Compilers for compiling computer programs and apparatuses including compilers are disclosed herein. A compiler may include one or more analyzers to parse and analyze source instructions of a computer program including identification of nested loops of the computer program. The compiler may also include a code generator coupled to the one or more analyzers to generate and output executable code for the computer program that executes on a data flow machine, including a data flow graph, based at least in part on results of the analysis. In embodiments, the executable code may include executable code that recursively computes predicates of identified nested loops for use to generate control signal for the data flow graph to allow execution of each loop to start when the loop's predicate is available, independent of whether any other loop is in execution or not. Other embodiments may be disclosed or claimed.

Loop execution with predicate computing for dataflow machines

Methods, apparatus, systems and articles of manufacture to map a set of instructions onto a data flow graph are disclosed herein. An example apparatus includes a variable handler to modify a variable in the set of instructions. The variable is used multiple times in the set of instructions and the set of instructions are in a static single assignment form. The apparatus also includes a PHI handler to replace a PHI instruction contained in the set of instructions with a set of control data flow instructions and a data flow graph generator to map the set of instructions modified by the variable handler and the PHI handler onto a data flow graph without transforming the instructions out of the static single assignment form.

Methods and apparatus to map single static assignment instructions onto a data flow graph in a data flow architecture

An apparatus for automatically converting a control flow program into a data flow program comprises a non-transitory machine-readable medium and a translator stored in the machine-readable medium. The translator, when executed by a data processing system, enables the data processing system to (a) automatically generate a control dependency graph for a control flow program, (b) automatically generate a data flow graph based at least in part on the control dependency graph, and (c) automatically generate a data flow program based at least in part on the data flow graph. In one embodiment or scenario, the translator may also automatically insert a switch instruction into the data flow program, in response to a determination that a variable of the control flow program is defined in one control dependency region and used in a different control dependency region. Other embodiments are described and claimed.

Growing community of inventors

Wayland, MA, United States of America

Yongzhi Zhang