Huawei Technologies Co., Limited

Future Wei Technologies, Inc.

Yongyao Li

Fei Luo

Jiang Zhu

Jiankang Li

Jun Yu

You Li

Gang Zhao

Xusheng Liu

Guoyu Wang

Howard S David

Er Nie

Shibin Xu

Yulong Ma

Wei Li

Liang Li

Lin Ma

Feng Wang

Yu Hu

Yuchun Lu

Sheng Li

Can Chen

Xin Qiu

Zhong Zhang

Yimin Yao

Shengyu Shen

Gongxian Jia

Xiaoyu Ge

Wei Kang

Zhongjian Chen

Liangyi Zhang

Nianbing Li

Jie Wan

Lv Chen

Xue Feng

Jiawu Liu

Jieping Zeng

Ruihui Hong

Embodiments of the present disclosure provide a method for optimizing a flash memory chip and a related apparatus. The method comprises, after completing write training of a nonvolatile flash interface (NFI) and establishing a data strobe signal (DQS) trigger point that triggers a memory to identify an electrical level state of a write data signal (DQ) corresponding to the DQS trigger point, determining whether a trigger condition for monitoring the NFI is met, wherein the trigger condition is related to working environmental data of the NFI; upon determining that the trigger condition for monitoring the NFI is met, writing test data to the memory and performing a margin test on the NFI to determine whether the NFI passes a margin test; and upon determining that the NFI does not pass the margin test, initiating interface retraining of the NFI. In this way, the NFI bus channels can be optimized without disk disconnection.

Method for optimizing flash memory chip and related apparatus

This application provides a memory training method, a memory controller, a processor, and an electronic device. The memory controller keeps transmission delays of N DQs unchanged, adjusts a transmission delay of a DQS, and determines a maximum DQS transmission delay and/or a minimum DQS transmission delay of the DQS when all data carried in the N DQs is correctly transmitted. The memory controller adjusts the transmission delay of the DQS to a target DQS transmission delay between the maximum DQS transmission delay and the minimum DQS transmission delay. The method helps quickly align relative timing positions between the DQS and the N DQs. Therefore, memory training may be repeatedly performed in a working process of the processor, so that the N DQs keep long enough timing margins.

Memory training method, memory controller, processor, and electronic device

This application provides a method for detecting margins of a data signal. A receive end of a data signal may adjust a voltage of a reference power source; adjust, based on a plurality of reference moments included in a reference moment set, a moment of an edge of a data strobe signal transmitted by a transmit end of the data signal; and during the adjustment, for each reference voltage and each reference moment, determine whether a bit error exists in data obtained by decoding the data signal when the voltage of the reference power source is the reference voltage and the moment of the edge of the data strobe signal is the reference moment, to obtain a timing margin of the data signal at each reference voltage and a voltage margin of the data signal at each reference moment.

Method and apparatus for detecting margins of data signal and storage device

This application provides an electronic module and an electronic device. The electronic module includes a first component, a second component, and a plurality of terminals. The first component includes a package substrate and a chip mounted on the package substrate. The second component includes a circuit board and a mount base mounted on the circuit board. Each terminal includes a body part, and a first bent part and a solder ball that are respectively connected to two opposite ends of the body part. In each terminal, the body part passes through and is fastened to the mount base, the first bent part presses against a corresponding first solder pad on the package substrate, and the solder ball is connected to a corresponding second solder pad on the circuit board.

Electronic module and electronic device

An equalization training method and apparatus are described. The method includes obtaining a training rate of each of a master chip and a slave chip in a target phase of equalization training. The method also includes determining a target rate threshold interval within which the training rate in the target phase falls, determining, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configuring the target equalization timeout period as an equalization timeout period in the target phase. According to this method, an equalization timeout period used for equalization training can be flexibly configured for each equalization training process, so that the configured equalization timeout period better conforms to a training rate currently used for link negotiation, to better ensure that an equalization parameter is found within the configured equalization timeout period, thereby improving an equalization training success rate.

Equalization training method and apparatus, and system

A chip module has a plurality of first ports, at least some or all of the first ports are first selection ports, and each first selection port may act as a write port or a read port. The chip module further includes a first control module. The first control module controls, based on a transmit/receive requirement of the chip module, the first selection port to be switched to a read port or a write port, to match the transmit/receive requirement of the chip module. The first selection port may selectively act as a read port or a write port, so that switching can be performed based on an operating state of the chip module, increasing a read/write bandwidth. The first control module controls an operating state of the first selection port, to flexibly adjust a quantity of read ports and a quantity of write ports of the chip module.

Chip module, communication system, and port allocation method

A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

System and method for receiver equalization and stressed eye testing methodology for DDR5 memory controller

This application provides a drive and a data transmission method, to implement low-latency transmission. The drive includes a CDR circuit, an elastic buffer, a receiver circuit, and a transmitter circuit. The CDR circuit is configured to recover a receive clock from a received signal. The receiver circuit is configured to recover sent data from the received signal by using the receive clock. The elastic buffer is configured to move the sent data in by using the receive clock and move the data out by using the receive clock. The transmitter circuit is configured to send the sent data from the elastic buffer by using the receive clock.

Drive and data transmission method

An equalization time configuration method is applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used. The equalization time configuration method includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

Equalization time configuration method, chip, and communications system

A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

Fast equalization method, chip, and communications system

A retimer application system is provided, which includes a primary chip, a retimer, and a secondary chip. After first link training is completed, the retimer is configured to store, in a first storage area, an equalization parameter corresponding to each rate during the first link training, and data stored in the first storage area is not lost when the retimer performs a reset operation. The retimer is further configured to: receive a reset indication, and perform the reset operation according to the reset indication. The primary chip and the secondary chip are configured to perform second link training triggered by the reset indication. During the second link training, the retimer is further configured to: invoke the equalization parameter, and transparently transmit a training sequence in the second link training to the primary chip or the secondary chip based on the equalization parameter.

Retimer application system, retimer, and data transmission method

Embodiments of this application disclose an encoding method and a related device. The method includes: receiving a to-be-encoded code block whose length is L, where L is a positive integer; and encoding the to-be-encoded code block to obtain a forward error correction FEC code, where a valid information length K of the FEC code is an integer multiple of a largest prime factor of L, and a total length N of the FEC code is a sum of K and a product of 2 and an error correction capability T of the FEC code. According to the embodiments of this application, it can be ensured that an FEC codeword satisfies a requirement for a low latency and a high gain.

Encoding method and related device

A controller for data strobe signal (DQS) position adjustment includes, when the controller obtains margin effective widths of all data signals in a transmission bus, it determines a left boundary and a right boundary based on the margin effective widths, where the left boundary is a largest value in minimum values of the margin effective widths of all the DQs, and the right boundary is a smallest value in maximum values of the corresponding margin effective widths when all the DQs are aligned with the left boundary. The controller calculates a first central position based on the left boundary and the right boundary, where the first central position is a center of a smallest margin effective width obtained after all the DQs are aligned during read data training, and adjusts a delay line (DL) of the DQS to the first central position.

DQS position adjustment method, controller and network device

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Shenzhen, China

Yongyao Li