Boe Technology Group Co., Ltd.

Hefei Xinsheng Optoelectronics Technology Co., Ltd.

Yongxian Xie

Tong Yang

Fengzhen Lv

Hui Wang

Xiaoye Ma

Feng Qu

Ran Zhang

Jideng Zhou

Yifeng Zou

Xingyi Liu

Zhixiang Zou

Mindong Zheng

Youlu Li

Chuanjiang Tang

Zhiyang He

Wei Feng

Xianjie Shao

Rui Ma

Rui Li

Xiaofeng Yin

Hui Guo

Qiang Liu

Jinliang Liu

Miao Zhang

Xiaowei Xu

Xiaofang Gu

Yongcan Wang

Ling Liu

Xiong Xiong

Chengying Cao

Yanchun Lu

Zhiwei Ding

Mingfei Zhang

Huanhuan Huang

Chuanfeng Deng

Jiale Li

Disclosed are a display substrate, a display panel and a display device. The display substrate includes: a base substrate, multiple gate-line groups, multiple data lines, the multiple data line include: first type of data lines and second type of data lines alternately arranged along the first direction; multiple transistors, transistors in the same sub-transistor group are connected with the same gate line, transistors in adjacent sub-transistor groups are connected with different gate lines, and transistors of the same sub-transistor group are connected with different data lines; multiple pins, the multiple pins include: first type of pins and second type of pins alternately arranged along the first direction; two adjacent first type of data lines are connected with a same first type of pin, and adjacent second type of data lines are connected with a same second type of pin.

Display substrate, display panel and display device

The embodiment of the present disclosure provides a display substrate including a plurality of gate lines and a plurality of data lines. The plurality of gate lines each extend along a first direction, and the plurality of data lines each extend along a second direction. The plurality of data lines are spatially crossed with the plurality of gate lines to define a plurality of pixel regions, and at least one sub-pixel is provided in each of the plurality of pixel regions. At least three sub-pixels adjacent to each other along the second direction form one of a plurality of pixels. All the sub-pixels within one of the plurality of pixels are coupled to a same data line of the plurality of data lines.

Display substrate and display device

An array substrate includes a base substrate, including a display area and a peripheral area; a driving circuit layer, located at one side of the base substrate and including a plurality of data lines and a plurality of scanning lines, where the plurality of data lines extend along a first direction and are arranged at intervals along a second direction, the plurality of scanning lines extend along the second direction and are arranged at intervals along the first direction, and the data line and the scanning line intersect with each other to define a plurality of sub-pixel areas; and a metal layer, located at one side of the driving circuit layer away from the base substrate, where the metal layer includes a plurality of metal blocks arranged at intervals, and the metal block is located at an intersection of the data line and the scanning line.

Array substrate and manufacturing method, display panel, and display device

A shift-register unit, a grid driving circuit and a displaying device, which relates to the technical field of displaying. In the present disclosure, the oxide-semiconductor layers of the oxide thin-film transistors may be delimited into regions according to the total channel widths and the channel lengths required by the oxide thin-film transistors in the shift-register unit, wherein the sum of the widths of the independent semiconductor branches obtained by the delimitation is equal to the required total channel width. Accordingly, one oxide thin-film transistor can realize the required total channel width by using the one or more semiconductor branches, to ensure the normal operation of the oxide thin-film transistor, whereby the oxide-semiconductor layers of the different oxide thin-film transistors can be configured differently, to realize the purpose of reducing the border frame of the displaying device.

Shift-register unit, grid driving circuit and displaying device

A shift register unit and a driving method thereof, a gate driving circuit, and a display device are provided. In the shift register unit, the input circuit inputs an input signal to a first node; the output circuit outputs an output signal to an output terminal; the first control circuit performs a first control on a level of a first control node; the first noise reduction control circuit controls a level of a second node; the second control circuit performs a second control on a level of a second control node; the second noise reduction control circuit controls a level of a third node; the first voltage-stabilizing circuit performs a third control on the level of the second control node, and the second control and the third control cause at least part of the second noise reduction control circuit to be in different bias states.

Shift register unit and driving method thereof, gate driving circuit, and display device

The present disclosure provides a shift register, a gate driving circuit and a display panel, and belongs to the field of display technology. The shift register of the present disclosure includes: an input circuit configured to precharge and reset a pull-up node; one pull-down control circuit being electrically connected to one pull-down circuit through a pull-down node; the pull-down control circuit being configured to control a potential at the pull-down node under a first power voltage; each pull-down circuit being configured to pull down the potential at the pull-down node in response to a potential at the pull-up node; an output circuit configured to output a clock signal through a signal output terminal in response to the potential at the pull-up node; one first noise reduction circuit connected to one pull-down node.

Shift register, gate driving circuit and display panel

The present disclosure discloses a shift register unit and a threshold voltage compensation method thereof, a driving circuit and a display apparatus. The shift register unit includes a cascaded output circuit coupled to a pull-up node, a clock signal input terminal, and a cascaded signal output terminal. The shift register unit is configured to transmit a clock signal from the clock signal input terminal to the cascaded signal output terminal under control of the pull-up node. A compensation circuit has a voltage output terminal coupled to the pull-up node, and is configured to provide an output voltage signal through the voltage output terminal during a blanking phase of a frame. The output voltage signal drives reverse drift of a threshold voltage of the cascaded output circuit.

Shift register unit and threshold voltage compensation method thereof, driving circuit and display apparatus

A shift register unit, a method of driving a shift register unit, a gate drive circuit, and a display device are provided. The shift register unit includes an input circuit, an output circuit, a first reset circuit, and a reset control circuit. The input circuit is configured to control a level of a first node; the output circuit is configured to output a clock signal to an output terminal; the first reset circuit is configured to reset the first node; and the reset control circuit is configured to input the first reset signal to the first reset circuit in response to a reset control signal and a reference signal, to turn on the first reset circuit and the reset control circuit is further configured to enable an amplitude of a level of the first reset signal to be larger than an amplitude of a level of the reference signal.

Shift register unit, method of driving shift register unit, gate drive circuit, and display device

A shift register unit, a driving method thereof, a gate driving circuit, and a display device are provided. The shift register unit includes an input branch and a reset branch; the input branch is configured to form or disconnect a first path between a first scan voltage terminal and a pull-up node under control of a potential of a first control terminal. The reset branch is configured to form or disconnect a second path between a second scan voltage terminal and the pull-up node under control of a potential of a second control terminal.

Shift register unit, driving method thereof, gate driving circuit and display device

The present disclosure provides a gate driving circuit, a current adjusting method thereof, and a display device. The gate driving circuit includes at least one gate driving sub-circuit. Each gate driving sub-circuit includes an output circuit and a current limiting circuit. The output circuit is configured to output a gate driving signal. The current limiting circuit is electrically connected to the output circuit. The current limiting circuit is configured to limit a current magnitude of the gate driving signal.

Gate driving circuit, current adjusting method thereof and display device

A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, an output circuit, and a first node control circuit. The input circuit is configured to charge a first node in response to an input signal; the output circuit is configured to output an output signal at an output terminal under control of a level signal of the first node; and the first node control circuit is configured to receive a precharge control signal from a precharge control terminal and charge the first node in response to the precharge control signal before the output terminal outputs the output signal.

Shift register unit comprising input circuit, output circuit, and first node control circuit, gate driving circuit, display device, and driving method

A shift register unit, a method of driving the same, a gate driving circuit and a display device are provided. The shift register unit includes a pull-up node control circuit, a first pull-down node control circuit, a second pull-down node control circuit, a pull-down node switching control circuit, and a gate driving output circuit. The pull-down node switching control circuit is configured to control the first control voltage signal to be written into the first pull-down node and control the second control voltage signal to be written into the second pull-down node under the control of a frame reset control signal. The gate driving output circuit is configured to control a gate driving signal outputted by a gate driving signal output terminal under the control of the voltage signal of the pull-up node, the voltage signal of the first pull-down node, and the voltage signal of the second pull-down node.

Shift register unit, method of driving the same, gate driving circuit and display device

A shift register unit including a first output circuit configured to transfer a clock signal at a clock signal terminal to a signal output terminal as an output signal in response to a first node being at an active potential, a second output circuit configured to transfer the clock signal at the clock signal terminal to a carry output terminal as a carry output signal in response to the first node being at the active potential, and a delay circuit configured to generate a delayed version of a carry input signal in response to the carry input signal at a carry input terminal being active, and to transfer an inactive voltage at a first voltage terminal to the signal output terminal in response to the delayed version of the carry input signal being active.

Shift register unit, gate driving circuit, display device and driving method

A gate drive circuit, a display device and a driving method are provided. The gate drive circuit includes a scan signal generation circuit and output control circuits in N stages. The scan signal generation circuit includes first output terminals in 2N stages, and is configured to output scan pulse signals in an order at the first output terminals in 2N stages; each of the output control circuits in N stages includes an input terminal, a first control terminal, a second control terminal, a second output terminal, and a bootstrap circuit, and is configured to control the bootstrap circuit, under control of a first control signal received by the first control terminal, an input signal received by the input terminal, and a second control signal received by the second control terminal, to output an output pulse signal with different pulse levels at the second output terminal.

Gate drive circuit, display device and method for driving gate drive circuit

This disclosure provides a method for treating an etching waste liquid from an etching process of indium tin oxide comprising hydrochloric acid, acetic acid, tin ions, indium ions and water, comprising the steps of: distilling the etching waste liquid to obtain a distillate comprising hydrochloric acid and acetic acid and a post-distillation liquid comprising tin ions and indium ions; generating a precipitate by reacting tin ions in the post-distillation liquid with sulfide ions to remove tin ions from the solution so as to obtain a post-precipitation solution containing indium ions; and electrolyzing the post-precipitation solution to obtain crude indium.

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Beijing, China

Yongxian Xie