Samsung Electronics Co., Ltd.

Yongseok Cho

Sanghoon Lee

Yohan Lee

Sunggil Kim

Woosung Lee

Suhyeong Lee

Kyong-Won An

Eunyeoung Choi

Hyunyong Go

An integrated circuit device includes a channel layer in a channel hole penetrating a conductive line and an insulating layer, a charge trap pattern inside the channel hole between the conductive line and the channel layer, and a dummy charge trap pattern inside the channel hole between the insulating layer and the channel layer. In order to manufacture the integrated circuit device, a channel hole penetrating an insulating layer and a mold layer is formed. A mold indent connected to the channel hole is formed. A preliminary dielectric pattern is formed in the mold indent. The preliminary dielectric pattern is oxidized to form a first blocking dielectric pattern. A charge trap layer is formed in the channel hole. The mold layer is removed to form a conductive space. A portion of the charge trap layer is removed to form charge trap patterns and dummy charge trap patterns.

Integrated circuit device and method of manufacturing the same

In a method of fabricating a semiconductor device, sacrificial layer patterns are formed by leaving portions of sacrificial layers, instead of completely removing the sacrificial layers. Thus, the reliability of the semiconductor device may be increased, and the process of manufacturing the same may be simplified.

Semiconductor device having sacrificial layer pattern with concave sidewalls and method fabricating the same

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Yongin-si, South Korea

Yongseok Cho