Samsung Electronics Co., Ltd.

Yongseok Ahn

Yoonyoung Choi

Jay-Bok Choi

Hyunyong Kim

Sangho Lee

Eunjung Kim

Joonkyu Rhee

Jiyoung Ahn

Seunghyung Lee

Jaybok Choi

Minsub Um

Kiseok Lee

Jemin Park

Myeong-Dong Lee

Junhyeok Ahn

Hyo-Sub Kim

Hyeonok Jung

Jamin Koo

Ju Hyung We

Provided is a semiconductor memory device comprising a device isolation pattern in a substrate and defining first and second active sections spaced apart from each other, wherein a center of the first active section is adjacent to an end of the second active section, a bit line that crosses over the center of the first active section, a bit-line contact between the bit line and the first active section, and a first storage node pad on the end of the second active section. The first storage node pad includes a first pad sidewall and a second pad sidewall. The first pad sidewall is adjacent to the bit-line contact. The second pad sidewall is opposite to the first pad sidewall. When viewed in plan, the second pad sidewall is convex in a direction away from the bit-line contact.

Semiconductor memory device

A semiconductor memory device includes a device isolation pattern on a substrate and defining a first active section, a first storage node pad on the first active section, a word line in the substrate and extending across the first active section, a bit line on the first storage node pad and crossing over the word line, a storage node contact on one side of the bit line and adjacent to the first storage node pad, and an ohmic layer between the storage node contact and the first storage node pad. A bottom surface of the ohmic layer is rounded.

Semiconductor memory device and method of fabricating the same

A semiconductor memory device includes a substrate including a device isolation pattern defining an active pattern extending in a first direction and including first and second source/drain regions, a word line extending in a second direction intersecting the first direction, a bit line that is on the word line and electrically connected to the first source/drain region and that extends in a third direction that intersects the first and second directions, a bit-line spacer on a sidewall of the bit line, a storage node contact electrically connected to the second source/drain region and spaced apart from the bit line across the bit-line spacer, and a dielectric pattern between the bit-line spacer and the storage node contact. The bit-line spacer includes a first spacer covering the sidewall of the bit line and a second spacer between the dielectric pattern and the first spacer.

A method of manufacturing an integrated circuit device includes: over a substrate, forming first hard mask patterns extending in a first direction parallel to a top surface of the substrate and arranged at a first pitch in a second direction; forming a plurality of first trenches in the substrate using the first hard mask patterns as etching masks; forming a plurality of first gate electrodes on inner walls of the plurality of first trenches; over the substrate, forming second hard mask patterns extending in the first direction and arranged at a second pitch in the second direction; forming a plurality of second trenches in the substrate using the second hard mask patterns as etching masks, each of the plurality of second trenches being disposed between two adjacent first trenches; and forming a plurality of second gate electrodes on inner walls of the plurality of second trenches.

Integrated circuit device and manufacturing method thereof

A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure covering a lower sidewall of the bit line structure, a contact plug structure on the active pattern and adjacent to the bit line structure, and a capacitor on the contact plug structure. The lower spacer structure includes first and second lower spacers that are sequentially stacked from the lower sidewall of the bit line structure in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower spacer includes an oxide, and contacts the lower sidewall of the bit line structure, but does not contact the contact plug structure, and the second lower spacer includes a material different from any of the materials of the first lower spacer.

Semiconductor devices

A semiconductor device includes a substrate having an active pattern, a cell region on the substrate and having a cell circuit, and a core region on the substrate having a peripheral circuit. In plan view, the active pattern on the core region includes a plurality of corners. Each of the corners has a rounding index that is equal to or less than about 15 nm. The rounding index is a distance between a respective tip of each of the corners and a right-angled corner.

Semiconductor device

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Seoul, South Korea

Yongseok Ahn