Boe Technology Group Co., Ltd.

Hefei Boe Joint Technology Co., Ltd.

Hefei Xinsheng Optoelectronics Technology Co., Ltd.

Beijing Boe Technology Development Co., Ltd.

Boe Technology Groupco., Ltd.

Boe Technology Group

Boe Technology Group Go., Ltd.

Yongqian Li

Xuehuan Feng

Zhidong Yuan

Can Yuan

Meng Li

Pan Xu

Zhongyuan Wu

Dacheng Zhang

Lang Liu

Quanhu Li

Zhenfei Cai

Dongxu Han

Cuili Gai

Song Meng

Min He

Xing Zhang

Yicheng Lin

Longyan Wang

Ling Wang

Chen Hui Xu

Tieshi Wang

Jingquan Wang

Wenchao Bao

Kun Cao

Yue Wu

Haixia Xu

Liu Wu

Yu Wang

Hao Liu

Cheng Xu

Chi Zhang

Baoxia Zhang

Fei Yang

Guoying Wang

Luke Ding

Jingwen Yin

Xuelian Cheng

Jinxia Hu

Chao Jiao

Xiuting Liu

Zehua Ding

Gang Wang

Guangcai Yuan

Ying Wang

Xing Yao

Miao Liu

Yuting Zhang

Qi Hu

Xiaolong Wei

Shi Sun

Yubao Kong

Enming Xie

Zhenhua Qiu

Lin Sun

Ming Wang

Wei Chen

Li Sun

Bin Zhou

Ning Liu

Ying Han

Leilei Cheng

Jingbo Xu

Miao Zhang

Chen Xu

Taejin Kim

Mingming Xie

A display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. The sub-pixels are arranged in a sub-pixel array in a first direction and a second direction, the first direction intersecting with the second direction. The display substrate further includes data lines extended in the first direction, and the data lines are connected in one-to-one correspondence with the sub-pixels in columns in each row of sub-pixels, so as to provide data signals respectively; the display substrate further includes auxiliary electrode lines extended in the first direction which are configured to be electrically connected with a second electrode of the light emitting element to provide a second power voltage; each of the auxiliary electrode lines is spaced from any one of the plurality of data lines by at least one column of sub-pixels.

Display substrate and display device

An array substrate is provided. The array substrate includes a plurality of subpixels and a plurality of detection line structures. The plurality of subpixels are arranged in an array of a plurality of rows and a plurality of columns along a first direction and a second direction. Each of the plurality of detection line structures includes at least one first detection line extending along the first direction; adjacent (n)th row and (n+1)th row of subpixels in the array form a subpixel row group, one detection line structure is provided between the (n)th row and (n+1)th row of subpixels in each subpixel row group, and the detection line structure is configured to be connected to the (n)th row and (n+1)th row of subpixels and detect electrical characteristics of first transistors or light-emitting elements in the subpixels.

Array substrate having signal line structures and power lines alternatively arranged one by one

A display panel and a display device are provided, the first signal line extends from the display region to the electrostatic discharge region in a first direction, and provides a first display signal to the sub-pixels; the electrostatic discharge units are arranged in the first direction, each electrostatic discharge unit includes a sub electrostatic discharge unit, each sub electrostatic discharge unit includes an electrostatic discharge circuit and a first conductor, the electrostatic discharge circuit is connected to the first signal line and the first conductor, and charges on the first signal line move towards the first conductor; the electrostatic discharge units include two adjacent electrostatic discharge units in a second direction perpendicular to the first direction, orthographic projections of the two adjacent electrostatic discharge units on a plane parallel to the first direction are not overlapped, and on a plane parallel to the second direction are overlapped.

Display panel and display device

A display substrate and a display device are provided. The display substrate includes: a plurality of pixel units arranged on a base substrate, each pixel unit includes a plurality of sub-pixels, and each sub-pixel includes a light emitting element and a pixel driving circuit; a semiconductor layer arranged on the base substrate; a first conductive layer arranged on a side of the semiconductor layer; and a second conductive layer arranged on another side of the semiconductor layer. The pixel driving circuit includes a driving transistor, a switching transistor and a sensing transistor; the switching transistor includes a first gate electrode and a first active layer; the display substrate further includes a channel defining portion for defining a channel region of the switching transistor, and an orthographic projection of the channel defining portion at least partially overlaps an orthographic projection of the first active layer on the base substrate.

A display substrate, a method for manufacturing the same, and a display apparatus are provided. The display substrate includes a base, and a pixel driving circuit and a bottom-emission light-emitting device that are arranged on the base and located in each sub-pixel in a display area. The light-emitting device includes a first electrode connected to the pixel driving circuit. The pixel driving circuit includes a first storage capacitor, the first storage capacitor includes a first storage electrode and a second storage electrode that are opposite to each other. The first electrode further serves as the first storage electrode, and the second storage electrode and the first electrode are both transparent electrodes.

Display substrate and method for manufacturing the same, and display apparatus

The present disclosure provides a shift register unit, including: a first sensing control input circuit and at least one first output circuit; the shift register unit further includes: a first voltage control circuit, a first sensing input leakage prevention circuit and a first current limiting circuit; the first sensing control input circuit is connected to a first pull-up node through the first sensing input leakage prevention circuit, the first sensing control input circuit is connected to the first sensing input leakage prevention circuit at a first sensing input leakage prevention node connected to a first voltage control node, the first sensing input leakage prevention circuit is connected to the clock control signal input terminal and is configured to control on/off between the first sensing input leakage prevention node and the first pull-up node; the first current limiting circuit is connected to the first voltage control node.

Shift register unit, gate driving circuit and display substrate

The present disclosure provides an array substrate and a display device. The array substrate includes a base substrate and a scan line, a data line, a power supply line, a sensing line, a pixel driving circuit and a light-emitting unit that are sequentially stacked on the base substrate. The array substrate also includes a gate layer, a first conductive layer, a second conductive layer, and a third conductive layer. The first electrode of the storage capacitor is at least disposed at the first conductive layer, and the second electrode of the storage capacitor is at least disposed at the second conductive layer. The data line, the power supply line, and the sensing line are disposed at the third conductive layer.

Array substrate and display device

A pixel circuit includes: a driving sub-circuit, a sensing sub-circuit, a light-emitting control sub-circuit, a sensing control sub-circuit, a light-emitting device and a sensing terminal. The driving sub-circuit includes a first terminal and a second terminal coupled to the light-emitting device, and is configured to write a data signal into the driving sub-circuit in response to a first scan signal and control an electrical signal flowing through the driving sub-circuit according to the data signal. The sensing sub-circuit is configured to connect the second terminal to the sensing terminal in response to a second scan signal. The light-emitting control sub-circuit is configured to connect a first voltage terminal to the first terminal in response to a light-emitting control signal. The sensing control sub-circuit is configured to connect a second voltage terminal to the first terminal in response to a sensing control signal provided by a sensing control terminal.

Pixel circuit, driving method of pixel circuit and display apparatus

Embodiments of the present disclosure provide a shift register, a gate drive circuit and a display device. The shift register includes a light emitting drive output module configured to supply a first voltage of a first power supply terminal to a light emitting control drive signal output terminal in response to control of a voltage at a third node, to supply a second voltage of a second power supply terminal to the light emitting control drive signal output terminal in response to control of a voltage at a second node, and to supply a second voltage of a second power supply terminal to the light emitting control drive signal output terminal in response to control of the second voltage at the second power supply terminal.

Shift register, gate drive circuit and display device

A pixel circuit and a driving method thereof, and a display device are disclosed. The pixel circuit includes a driving circuit, a data writing circuit, a reset circuit, a light-emitting control circuit and a light-emitting element. The driving circuit includes a control terminal, a first terminal and a second terminal; the data writing circuit is connected to a first node to apply a data voltage; the reset circuit is connected to the first node to apply a reference voltage. The pixel circuit further includes a partition control circuit, which is connected to the first node and the control terminal, and is configured to apply the data voltage and the reference voltage to the control terminal; the reset circuit is connected to one of the first terminal and the second terminal of the driving circuit, and the reset circuit is further configured to apply an initialization voltage to the driving circuit.

Pixel circuit and driving method thereof, and display device

A shift register circuit includes an input sub-circuit, an output sub-circuit, a control sub-circuit and a compensation sub-circuit. The input sub-circuit is configured to, under control of a first input signal received at a first input signal terminal, transmit the first input signal to a pull-up node. The output sub-circuit is configured to transmit a first clock signal received at a first clock signal terminal to a first signal output terminal under control of a voltage at the pull-up node. The control sub-circuit is configured to transmit a voltage at a first reference node to the pull-up node under control of a first control signal received at a first control signal terminal. The compensation sub-circuit is configured to transmit a voltage at a seventh node to the pull-up node under control of a seventh clock signal received at a seventh clock signal terminal.

Shift register circuit, gate driver circuit and driving method therefor, and display apparatus

The present disclosure provides a signal selection circuit and a signal selection method of a display panel, and a display device. The display panel has N regions and includes pixel driving circuits and M gate driving circuits for providing M gate driving signals to the pixel driving circuits; each gate driving circuit includes N gate driving sub-circuits, each of which is configured to provide one gate driving signal to the pixel driving circuits in one region; M≥2, N≥2, and M and N are integers; the signal selection circuit includes: M frame start signal lines, each of which is configured to provide a frame start signal for one gate driving circuit; and a selection sub-circuit configured to output frame start signals written by the frame start signal lines to the gate driving sub-circuits corresponding to the regions of the display panel according to a preset sequence.

Signal selection circuit and method of display panel, and display device

The present disclosure provides a display device, a gate drive circuit, a shift register unit and a driving method thereof. The shift register unit includes an input subcircuit configured to control a voltage at the first node under voltage control of the input control end; a signal output subcircuit configured to control disconnection and conduction between the clock signal ends and respective signal output ends under voltage control of the first node; a first control subcircuit configured to control the voltage at the first node under voltage control of the first control signal end.

Display device, gate drive circuit, shift register unit and driving method thereof

A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-circuit, a second sub-circuit, a leakage prevention circuit and a blanking input sub-circuit, wherein the first sub-circuit includes a first input circuit and a first output circuit; the second sub-circuit includes a second input circuit and a second output circuit; the leakage prevention circuit is configured to control a level of a leakage prevention node under control of the level of the first node, so as to turn off a circuit connected between the first node and the leakage prevention node; and the blanking input sub-circuit is connected to the first node and the second node, and is configured to receive a selection control signal and a first clock signal, and control the level of the first node and the level of the second node.

Shift register unit, gate driving circuit, display device and driving method

The present disclosure provides a display substrate and a display device, and belongs to the field of display technology. The display substrate of the present disclosure has a display region, and includes a base and a plurality of data lines and a plurality of fan-out traces on the base; each of the plurality of data lines is connected to a corresponding one of the plurality of fan-out traces at a connection node in the display region; and at least one of the plurality of data lines is connected to a corresponding fan-out trace at a plurality of connection nodes.

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Beijing, China

Yongqian Li