Sandisk Corporation

Atmel Corporation

Artemis Acquisition LLC

Sandisk Technologies Inc.

Chengdu Monolithic Power Systems Co., Ltd.

Yongliang Wang

Danut Manea

Stephen Trinh

Jeff Kotowski

Po-Shen Lai

Paul Hill

John Pasternak

Richard V De Caro

Scott N Fritz

Daniel P Nguyen

Sean S Chen

Raul Adrian Cernea

Lijie Jiang

Chi-Ming Wang

Paul A Lassa

Ekram Bhuiyan

Steve Chi

Tao Zhao

Paul Paternoster

Binci Xu

Vincent Anthony Condito

Liwei Liu

Ekram Hossain Bhuiyan

Steve X Chi

Richard V Caro

A voltage regulator provides an output voltage and an output current. The output voltage decreases with an increase of the output current when the output current is lower than a current breaking point, and the output voltage is maintained when the output current reaches the current breaking point.

Voltage regulators with controlled output voltage and the method thereof

In a bandgap voltage reference with low package shift, a proportional to absolute temperature (PTAT) voltage is generated using a single diode biased at two different current levels at two different times. Using the same diode for both current density measurements removes the absolute value of the base-emitter junction voltage (Vbe) and any package shift in the PTAT voltage. The bandgap voltage reference can be implemented in a single or differential circuit topology. In some implementations, the bandgap voltage reference can include circuitry for curvature correction.

Voltage reference with low sensitivty to package shift

A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down.

Ultra-deep power-down mode for memory devices

An adaptive phase-lead compensation (zero) circuit is disclosed that can be added to a circuit (e.g., a CMOS-based LDO) to ease the compensation and increase the phase margin of the circuit. By using the disclosed adaptive phase-lead compensation circuit, an adjustable resistance can be connected to any nodes in the compensated circuit rather than just to the voltage source (VDD) or ground (GND), allowing the Miller Effect to be used via a Miller capacitor.

Adaptive phase-lead compensation with Miller Effect

Voltage reference with low sensitivity to package shift

A plurality of separately powered data interface circuits, a controller circuit, and power switch circuits that collectively enable a supply of power to only one of the data interface circuits and disable the supply of power to the other data interface circuits. Alternatively, the separately powered circuits need not be data interface circuits.

Selectively powered data interfaces

A new approach for managing turn-on of power islands uses a precharge phase to begin the process of bringing up the island's internal supply voltage, while minimizing transients and associated power-control-logic instability.

Systems, methods, and integrated circuits with inrush-limited power islands

A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

Self-configurable multi-regulator ASIC core power delivery

A step down voltage regulator with bypass comprised of devices designed to operate over a maximum rated voltage lower than a supply voltage. The regulator includes an output regulation device coupled to the supply voltage and an output. An output device protection circuit is provided which is responsive to the supply voltage and the output to ensure that the maximum rated voltage of the output regulation device is not exceeded. A bypass circuit having a bypass output device and being coupled to the supply voltage is provided with a protection circuit. The output regulation devices comprise p-channel transistors, and may have an operating maximum rated voltage in a range of 2.7-3.6 volts with the supply voltage is in a range of 4.4-5.25 volts, or 2.9-3.5 volts.

Voltage regulator with bypass mode

A step down voltage regulator including devices designed to operate over a maximum rated voltage lower than the supply voltage. The regulator comprises an output regulation device coupled to the supply voltage and an output; and an output device protection circuit responsive to the supply voltage and the output to ensure that the maximum rated voltage of the output device is not exceeded. Also provided is a method for operating a voltage regulator in a memory system. The method includes the steps of: providing a voltage regulator having an input and an output, and including a plurality of devices operating at a maximum rated voltage less than the voltage provided at the input; and controlling the gate voltage of the output device responsive to a load on the regulator output, so that the maximum rated voltage is not exceeded.

Voltage regulator using protected low voltage devices

Techniques for producing and utilizing temperature compensated voltages to accurately read signals (e.g., voltages) representing data stored in memory cells of a memory system are disclosed. The memory system is, for example, a memory card. The magnitude of the temperature compensation can be varied or controlled in accordance with a temperature coefficient. These techniques are particularly well suited for used with memory cells that provide multiple levels of storage.

Voltage generation circuitry having temperature compensation

Growing community of inventors

Saratoga, CA, United States of America

Yongliang Wang