Chinese Academy of Sciences

Fairchild Semiconductor Corporation

International Business Machines Corporation

Peking University

China Electric Power Research Institute

State Grid Cooperation of China

Yongliang Li

Qiuxia Xu

Wenwu Wang

Xiaohong Cheng

Lei Huang

Huaxiang Yin

Tawei Hu

Gerald Edward Kozina

Phong Kim Truong

Qingzhu Zhang

Peng Zhu

Iun Veng Leong

George Francis Silva

Masoud Madani

Jun Luo

Kenneth Patrick Snowdon

Xiaohong Zhang

Fei Zhao

Julie Lynn Stultz

Seth M Prentice

Gaobo Xu

Hui Yu

Shawn Barden

Taeghyun Kang

Zhiyuan Li

Shicheng Wei

Kenneth O'Brien

Ping Zhou

Jianing Zhou

Guofu Li

Graham L S Connolly

Mengke Wang

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes: a substrate and a channel portion. The channel portion includes a first portion including a fin-shaped structure protruding with respect to the substrate and a second portion located above the first portion and spaced apart from the first portion. The second portion includes one or more nanowires or nanosheets spaced apart from each other. Source/drain portions are arranged on two opposite sides of the channel portion in a first direction and in contact with the channel portion. A gate stack extends on the substrate in a second direction intersecting with the first direction, so as to intersect with the channel portion.

Semiconductor device having high driving capability and steep subthreshold swing (SS) characteristic and method of manufacturing the same

A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.

Stacked nanowire or nanosheet gate-all-around device and method for manufacturing the same

A semiconductor device, including: a silicon substrate; multiple fin structures, formed on the silicon substrate, where each extends along a first direction; a shallow trench insulator, located among the multiple fin structures; a gate stack, intersecting with the multiple fin structures and extending along a second direction, where first spacers are formed on two sidewalls in the first direction of the gate stack; source-or-drain regions, formed on the multiple fin structures, and located at two sides of the gate stack along the first direction; and a channel region, including a portion of the multiple fin structures located between the first spacers. and notch structures. A notch structure recessed inward is located between each of the multiple fin structures and the silicon substrate. The notch structure includes an isolator that isolates each of the multiple fin structures from the silicon substrate.

Semiconductor device and method for manufacturing the same

The invention provides a device and the use thereof in a cell experiment in vitro. This device has a polydopamine layer-carboxymethyl chitosan layer-peptide layer structure, which is capable of regulating behaviors of human pluripotent stem cells and is useful in cell culture or a cell experiment in vitro.

Device and use thereof in cell experiments in vitro

Provided are techniques for movement readiness checking. It is determined whether each content object in a set of content objects is ready for movement. For each content object in the set of content objects that is determined to be ready for movement, an associated movement readiness indicator is set to indicate that the content object is ready to be moved. Then, each content object in the set of content objects is moved that has the associated movement readiness indicator set to indicate that the content object is ready to be moved.

Readiness checker for content object movement

The present invention provides an online monitoring circuit of the series compensation spark gap divider return circuit. Said series compensation spark gap divider return circuit includes a voltage equalization link and a voltage sampling link. Said voltage link includes the capacitor C which series said voltage equalization link. Said online monitoring circuit includes the voltage sampling input module, series compensation current input module and the compare module. Said sampling voltage input module after amplified the voltage of the two ends of the series capacitor C converts it into direct current signal.

Online monitoring circuit and method of the series compensation spark gap divider return circuit

This document discusses, among other things, an electro-static discharge (EDS) filtering circuit and method, a reset circuit, and an electronic device. The ESD filtering circuit comprises a first current dividing circuit and a second current dividing circuit which respectively share a current of a first power source signal and aggregate the shared currents to form a second power source signal upon filtering, wherein a voltage drop of the first current dividing circuit is constant and the second current dividing circuit is a pure resistor element circuit.

Electro-static discharge filtering circuit and method, reset circuit, and electronic device

End of retention processing is provided. Included is: creating, using a content manager (CM), an end of retention policy for a content in a database management system (DBMS; and creating, based on the end of retention policy, a stored procedure in the DBMS for managing the end of retention policy.

End of retention processing using a database manager scheduler

A controller receives a request from a user to store content in a target node of a plurality of nodes. A determination is made of a preferred node for the user, from a repository that maintains a correspondence between the user and the preferred node for storing the content for the user, wherein the preferred node is included in the plurality of nodes. Responsive to determining from that the determined preferred node is the target node, the controller transmits the request from the user to store the content, to the preferred node. Responsive to determining that the determined preferred node is not the target node, the controller transmits the request and an identification of the target node to the preferred node.

Method, system, and computer program product to update content on networked cache servers

This document discusses, among other things, a biased electrostatic discharge (ESD) circuit and method configured to reduce capacitance of an ESD structure with little to no change in other ESD structure parameters. A bulk terminal of an ESD device can be negative biased to reduce a drain terminal to source terminal capacitance of the ESD device. A charge pump can be configured to provide a negative bias to the bulk terminal of the ESD device. In certain examples, the gate terminal of the ESD device can be coupled to the source terminal of the ESD device, such as through a resistor, and the source terminal can be coupled to ground.

Biased ESD circuit

This document discusses, among other things, an impedance detection circuit, method, and integrated circuit, comprising a ramp-up current generation circuit and an impedance determining circuit, wherein the ramp-up current generation circuit is configured to input a ramp-up current including n breaks to a port of a device where the ramp-up current generation circuit is disposed, to which port an external device is connected, and wherein the impedance determining circuit is configured to detect an impedance of the external device in each break time period of the ramp-up current input by the ramp-up current generation circuit until the impedance of the external device is acquired by detection in the last break time period of the n breaks.

Impedance detection circuit, method, and integrated circuit

This document discusses, among other things, a detection system configured to identify a type of a pole of a four-pole audio jack using first and second comparators. The detection system can include a bias circuit configured to bias a detection input coupled to the pole, and first and second comparators configured to compare the detection input to respective first and second thresholds to provide an indication of the type of the pole.

Audio jack detection circuit

The disclosure provides a clamp circuit and a method for clamping voltage. The clamp circuit includes: a first switch control unit, connected with the high-potential terminal of the first stage output of a comparator and configured to clamp the voltage of the high-potential terminal to Vwhen the voltage of the high-potential terminal is lower than a first pre-set value V, and a second switch control unit, connected to the low-potential terminal of the first stage output of the comparator and configured to clamp the voltage of the low-potential terminal to Vwhen the voltage of the low-potential terminal is higher than a second pre-set value V, wherein the voltages of the first stage output of the comparator are between Vand V. By the disclosure, the output voltage swings of the first stage of the comparator are limited, and thereby the processing speed of the comparator is improved.

Clamp circuit and method for clamping voltage

A method for manufacturing a metal gate stack structure in gate-first process comprises the following steps after making conventional LOCOS and STI isolations: growing an untra-thin interface layer of oxide or oxynitride on a semiconductor substrate by rapid thermal oxidation or chemical process; depositing a high dielectric constant (K) gate dielectric on the untra-thin interface oxide layer and then performing rapid thermal annealing; depositing a TiN metal gate; depositing a barrier layer of AlN or TaN; depositing a poly-silicon film and a hard mask, and performing photo-lithography and the etching of the hard mask; after photo-resist removing, etching the poly-silicon film/metal gate/high-K gate dielectric sequentially to form the metal gate stack structure. The manufacturing method of the present invention is suitable for integration of high-K dielectric/metal gate in nano-scale CMOS devices, and removes obstacles of implementing high-K/metal gate integration.

Growing community of inventors

Beijing, China

Yongliang Li