Western Digital Technologies, Inc.

Skhynix Inc.

Carnegie Mellon University

Yongjune Kim

Cyril Guyot

Won Ho Choi

Yuval Cassuto

Robert Eugeniu Mateescu

Zvonimir Z Bandic

Seung-Hwan Song

Martin Lueker-Boden

Yoocharn Jeon

Vijayakumar Bhagavatula

Kyungjin Kim

A system and method for training base classifiers in a boosting algorithm includes optimally training base classifiers considering an unreliability model, and then using a scheme with an aggregator decoder that reverse-flips inputs using inter-classifier redundancy introduced in training.

Training ensemble models to improve performance in the presence of unreliable base classifiers

Certain aspects of the present disclosure provide a method for performing multimode inferencing, comprising: receiving machine learning model input data from a requestor; processing the machine learning model input data with a machine learning model using processing hardware at a first power level to generate first output data; selecting a second power level for the processing hardware based on comparing the first output data to a threshold value; processing the machine learning model input data with the machine learning model using the processing hardware at the second power level to generate second output data; and sending second output data to the requestor.

Variable power mode inferencing

Methods and apparatus are disclosed for implementing principal component analysis (PCA) within a non-volatile memory (NVM) die of solid state drive (SSD) to reduce the dimensionality of machine learning data before the data is transferred to other components of the SSD, such as to a data storage controller equipped with a machine learning engine. The machine learning data may include, for example, training images for training an image recognition system in which the SSD is installed. In some examples, the on-chip PCA components of the NVM die are configured as under-the-array or next-to-the-array components. In other examples, one or more arrays of the NVM die are configured as multiplication cores for performing PCA matrix multiplication. In still other aspects, multiple NVM dies are arranged in parallel, each with on-chip PCA components to permit parallel concurrent on-chip processing of machine learning data.

Non-volatile memory with on-chip principal component analysis for generating low dimensional outputs for machine learning

Disclosed herein is an apparatus for estimating randomness of a random number generator. The apparatus is configured to divide output data (), generated by the random number generator (), into blocks () of a length (L), estimate a Shannon entropy of a second sub-set () of the blocks (), using a first sub-set () of the blocks () to initialize the estimating, solve an estimate function, that relates an argument parameter (&#x3b8;) to the Shannon entropy estimate, to determine a value for the argument parameter (&#x3b8;) that is indicative of a probability of a most probable block being generated by the random number generator () as a new block, and use the length (L) to tune an estimate of randomness of the random number generator () calculated based on the value for the argument parameter (&#x3b8;).

Efficient estimator of min-entropy

A system and method for allocating computational resources includes a plurality of classifiers, a memory array, and a memory controller to allocate memory from the memory array to each of the plurality of classifier. The system and method also include an optimization processor to determine an optimized bit precision value for at least one of the plurality of classifiers based upon a relative importance of the plurality of classifiers. The memory controller allocates the memory from the memory array to the plurality of classifiers based upon the determined optimized bit precision value.

Computational resource allocation in ensemble machine learning systems

An apparatus is provided that includes a memory device including a plurality of sub-arrays, and a memory controller. The memory controller is configured to determine a value of a parameter of a corresponding write pulse for each bit of a word based on a relative importance of each bit, and write each bit of the word to a corresponding one of the plurality of sub-arrays using the corresponding write pulses.

Apparatus and methods for writing random access memories

Disclosed are devices, systems and methods for improving the reliability of retrieving information from a memory device. An exemplary method includes obtaining a plurality of cell counts for each of a plurality of read voltages applied to the memory device, each of the plurality of cell counts representing a number of cells having a cell voltage value that is within a voltage band corresponding to the read voltage applied thereto, generating, based on the plurality of cell counts, the plurality of read voltages and a design parameter, a set of estimated parameters, the design parameter being based on one or more properties of the memory device, determining an updated read voltage based on the estimated set of parameters, and applying the updated read voltage to the memory device to retrieve the information from the memory device.

Robust detection techniques for updating read voltages of memory devices

A system and method include determining, by a memory controller associated with a memory device, a value of a parameter of a write pulse for a plurality of bits of a B-bit word to be stored in the memory device. The value of the parameter is based upon a relative importance of a bit position of the plurality of bits in the B-bit word to a performance of a machine learning or signal processing task involving the B-bit word, a fidelity metric, and a resource metric. The system and method also include writing each of the plurality of bits of the B-bit word in a different sub-array of the memory device using the write pulse generated based on the value of the parameter determined for a particular one of the plurality of bits.

Write efficiency in magneto-resistive random access memories

A system and method for refreshing memory cells of a memory device includes storing each bit of a B-bit word in a different sub-array of a memory device. Each of the bits is associated with a bit position, and the memory device includes a plurality of sub-arrays. The system and method also include determining a refresh interval for a plurality of the bit positions based upon a relative importance of the plurality of the bit positions to a performance of a machine learning or signal processing task involving the B-bit word. The refresh interval is based upon a fidelity metric and a resource metric. The system and method further include refreshing the plurality of sub-arrays based upon the refresh interval determined for the plurality of bit positions, and dynamically updating the refresh interval for the plurality of bit positions upon receiving a new fidelity metric or a new resource metric.

Granular refresh rate control for memory devices based on bit position

A method includes, in one aspect, performing a read operation on a wordline of a memory device, wherein the wordline comprises a plurality of cells that are expected to be in a first state; based on the read operation, identifying one or more of the plurality of cells that are determined to be in a second state that differs from the first state; encoding data using information pertaining to the identified cells to generate a codeword comprising a plurality of bits to be written to the wordline, with at least one of the plurality of bits, which are to be written to at least one of the identified cells, having a value corresponding to the second state; and writing the generated codeword to the wordline.

Reducing errors caused by inter-cell interference in a memory device

Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including determining whether the memory includes a defective memory cell, receiving a message to be written to the memory, sub-dividing the message into a plurality of sub-messages, generating a first error correction code for the sub-messages, the first error correction code being a first type, generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes, and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.

Error correction for non-volatile memory

Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including writing first data to the memory, reading the first data from the memory, analyzing the first read data such that the analyzing includes determining whether the read data includes an error, encoding second data based on the analyzing of the first data such that the second data is encoded to be written to a position adjacent to the error when it is determined that the read data includes the error, and writing the encoded second data to the memory at the position.

Growing community of inventors

San Jose, CA, United States of America

Yongjune Kim