Semitronix Corporation

Yongjun Zheng

Weiwei Pan

Xu Ouyang

Zheng Shi

Fan Lan

Shenzhi Yang

Peiyong Zhang

Kangpeng Shao

Yongli Liu

Lili Li

A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

Addressable test chip

To improve test efficiency of addressable test chips, an addressable test chip test system includes a test equipment, a probe card and an addressable test chip, the test equipment connects to the addressable test chip through the probe card to constitute a test path, the test system includes a new type of address register, which can provide two test modes for users according to user's needs. A new type of high density addressable test chip can accommodate DUTs of more than 1000/mm.

Addressable test chip test system

An addressable ring oscillator test chip includes: a plurality of ring oscillator test units, and a peripheral structure including peripheral circuits and PADs. The peripheral circuits share a first power source and a first grounding. Each test unit is associated with an independent power source to thereby decrease voltage drop resulting from wiring and to reduce the influence from other test units. A method of generating a variety of ring oscillators includes: generating a cell template corresponding to a basic unit, including defining a parameterized cell template; generating a ring oscillator based on the cell template, including generating ring oscillators of different stages by selecting different parameters of the cell template; realizing internal connections of the ring oscillator; and generating an instantiated ring oscillator by replacing cell templates with corresponding basic units.

Addressable ring oscillator test chip

An addressable test circuit is configured to test parameters of a plurality of transistors. The addressable test circuit includes combination logic circuits including a plurality of gate circuits and are configured to select a device under test, a plurality of PADs, a plurality of address bus and data bus; wherein six or more of the data buses are test signal lines. A test method can employ the above address test circuit for testing parameters of a plurality of transistors, where the subthreshold leakage current Iand saturation current Iare measured in different signal lines respectively to ensure the accurate measurement of the two parameters in one circuit.

Addressable test circuit and test method for key parameters of transistors

A programmable test chip includes a target chip to be tested and addressing circuits fabricated on the same wafer. The addressing circuits can be placed in the scribe lines or a pre-allocated area of the wafer. When testing the target chip, a circuit connecting the target chip and the addressing circuits can be fabricated on demand. In some cases the target chip is not connected to the addressing circuits, and a DUT array exists in a scribe line having a connecting circuit prefabricated between the addressing circuits with the DUT array for testing the DUT array in the scribe line. When the need for testing the target chip arises, the prefabricated connecting circuit can be cut, and the connecting circuit connecting the target chip and the addressing circuits can be fabricated. Based on results from such test chips, the manufacturing process can be better studied.

Programmable addressable test chip

The present invention relates to the chip testing field. A method for testing a plurality of transistors in a target chip is provided, characterized by automatically selecting a plurality of pre-defined transistors on the target chip and adding a connection layer to the key layers of each transistor such that the transistor to be tested is connected with and measured by an outside tester. Through automatic generation of the test structures and automatic wiring, the present invention greatly shortens the design cycle of test chips for target transistor testing, and greatly reduces the error probability in the process of designing test chips for target transistor testing, and improves the testing relevancy.

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Hangzhou, China

Yongjun Zheng