Micron Technology Incorporated

Intel Corporation

Other

Yongjun Jeff Hu

Everett Allen McTeer

Allen McTeer

Shu Qin

Tsz Wah Chan

Christopher W Petz

Daniel Billingsley

Durai Vishak Nirmal Ramaswamy

Li Li

Swapnil Lengade

Jordan D Greenlee

John Mark Meldrim

Er-Xuan Ping

Scott Jeffrey DeBoer

Pengyuan Zheng

Haoyu Li

Scott E Sills

Gary Chen

David Ross Economy

John David Hopkins

Randhir P S Thakur

Michael L Nuttall

Yiping Wang

Lequn Jennifer Liu

Salman Akram

Luan C Tran

Ravi T Iyer

Pai-Hung Pan

Whonchee Lee

Matthew J King

Brent D Gilgen

Qian Tao

Martin F Schubert

Jigish D Trivedi

Ronald Allen Weimer

Zhongze Wang

Dale Collins

Pai Hung Pan

James Beck

Deepa Ratakonda

Randhir P Thakur

Rita J Klein

Yushi Hu

Wei Yeeng Ng

Andrew Li

Robert K Grubbs

Kent H Zhuang

Shanming Mou

H Jim Fulford

Haitao Liu

Gordon A Haller

Roger W Lindsay

Anish A Khandekar

Andrew Bicksler

David A Kewley

Andrea Gotti

Robert J Hanson

Hongqi Li

Farrell Martin Good

Vladimir Mikhalev

Zhenyu Lu

Suresh Ramarajan

Xiaosong Zhang

Sidhartha Gupta

Luca Fumagalli

Santanu Sarkar

Kentaro Ishii

Kyle A Ritter

Naga Chandrasekaran

Keen Wah Chow

Tom George

Biow Hiem Ong

Amirhasan Nourbakhsh

Rajesh Balachandran

Brian S Beatty

Jay Steven Brown

Michael J Irwin

Amritesh Rai

Md Zahid Hossain

Yao Jin

Gurtej S Sandhu

John A Smythe

Lorenzo Fratin

Kevin J Torek

Jiutao Li

Enrico Varesi

Jaydeb Goswami

Lijing Gou

Russell A Benson

Satish Bedge

Jennifer Lequn Liu

Ying Rui

Qi Pan

Tsz-Wah Chan

Caizhi Xu

Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.

Memory device with low density thermal barrier

A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier. After the stop, the sacrificial material is removed from the lower channel openings and channel-material strings are formed in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.

Integrated circuitry comprising a memory array comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

Memory circuitry comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Charge-passage material is in the conductive tiers laterally-outward of the channel-material strings. Storage material is in the conductive tiers laterally-outward of the charge-passage material. At least one of AlOq, ZrOq, and HfOq is in the conductive tiers laterally-outward of the storage material. At least one of (a) and (b) is in the conductive tiers laterally-outward of the at least one of AlOq, ZrOq, and HfOq, where, (a): MoON, where each of 'x' and “y” is from 0 to 4.0; and (b): MoM, where “M” is at least one of W, a Group 7 metal, and a Group 8 metal; “z” being greater than 0 and less than 1.0. Metal material is in the conductive tiers laterally-outward of the at least one of the (a) and the (b). Memory cells are in individual of the conductive tiers. The memory cells individually comprise the channel material of individual of the channel-material strings, the storage material, the at least one of AlOq, ZrOq, and HfOq, the at least one of the (a) and the (b), and the metal material. Other embodiments are disclosed.

Transistor and memory circuitry comprising strings of memory cells

A variety of applications can include apparatus having a memory device structured with an array of memory cells and a complementary metal-oxide-semiconductor (CMOS) device coupled to the array. The CMOS device can include a gate electrode on and contacting the polysilicon gates of a p-channel metal-oxide-semiconductor (PMOS) transistor and a n-channel metal-oxide-semiconductor (NMOS) transistor of the CMOS device, where the gate electrode is a multi-metal stack. The multi-metal stack of the gate electrode can be two levels of different metal compositions.

Metal gate stacks for CMOS scaling

Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

Semiconductor constructions, methods of forming transistor gates, and methods of forming NAND cell units

A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b). Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-first-tier or said lower upper-first-tier. After the stop, the sacrificial material is removed from the lower channel openings and form channel-material strings in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.

Integrated circuitry comprising a memory array comprising strings of memory cells and comprising a stack containing non-stoichiometric silicon nitride

Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 10atoms/cmto about 10atoms/cm. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of β-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.

Microelectronic devices and memory devices including conductive levels having varying compositions

A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

Microelectronic devices including conductive structures

In a variety of processes for forming electronic devices that use spin-on dielectric materials, properties of the spin-on dielectric materials can be enhanced by curing these materials using plasma doping. For example, hardness and Young's modulus can be increased for the cured material. Other properties may be enhanced. The plasma doping to cure the spin-on dielectric materials uses a mechanism that is a combination of plasma ion implant and high energy radiation associated with the species ionized. In addition, physical properties of the spin-on dielectric materials can be modified along a length of the spin-on dielectric materials by selection of an implant energy and dopant dose for the particular dopant used, corresponding to a selection variation with respect to length.

Plasma doping of gap fill materials

An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.

Apparatus and memory device including conductive lines and contacts, and methods of forming an apparatus including conductive lines and contacts

A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.

Semiconductor devices comprising threshold switching materials

Growing community of inventors

Boise, ID, United States of America

Yongjun Jeff Hu