Samsung Electronics Co., Ltd.

Yongjoo Song

Chulho Choi

Hajoon Shin

Jinwoo Kim

Hajun Lee

Jeongah Ahn

Jiyong Jeong

Youngsub Jin

Sung-Ho Lee

Sungjin Lim

Ju-hyun Ko

Jin-woo Kim

Kyunlyeol Lee

Jia-Way Chen

Yu-Wen Chiou

Beophee Kim

Hanchiang Su

Yichien Wen

Jia Wei Chen

Pan-soo Kim

Shih Chiao Huang

Yu-chieh Huang

Tao-Jung Hung

Han-chiang Su

Myungho Seo

Yi-chien Wen

Ying-Da Chang

Chao Hsuan Liu

Zhen-Guo Ding

Jia-way Chen

Shih-Hsiung Kuo

Shih-chiao Huang

Ching-Chieh Wu

Chui-Hsun Chiu

Yu-Chieh Huang

A display driving circuit is provided. The circuit drives a display panel that includes data lines, sensing lines, and sub-pixels connected to the data lines and the sensing lines. The display driving circuit includes a data driver integrated circuit that drives the data lines. The data driver integrated circuit includes a driving block and a sensing block. The driving block includes plural digital-analog converters (DACs) each performing digital-analog conversion with respect to received sub-pixel data to generate output voltages and provide the output voltages of the DACs to the data lines. The sensing block measures grayscale voltages output from the DACs in a first operation mode and measures pixel voltages of the sub-pixels received from the sensing lines in a second operation mode.

Display driving circuit and operating method thereof

A gamma tap circuit includes: (i) a first gamma division circuit configured to generate a first gamma tap voltage by performing voltage division of an upper gamma tap voltage and a lower gamma tap voltage, in-sync with a first clock signal CKand a first complementary clock signal CK, which is 180° out-of-phase relative to CK, (ii) a second gamma division circuit configured to generate a second gamma tap voltage by performing voltage division of the upper gamma tap voltage and the first gamma tap voltage, in-sync with a second clock signal CKand a second complementary clock signal CK, which is 180° out-of-phase relative to CK, and (iii) a third gamma division circuit configured to generate a third gamma tap voltage by performing voltage division of the first gamma tap voltage and the lower gamma tap voltage, in response to CKand CK, which have a lower frequency relative to CKand CK

Gamma tap voltage generating circuits and display devices including the same

The present disclosure provides methods, apparatuses, and non-transitory computer-readable mediums for setting charge sharing times, which may be adaptable to a display panel. In some embodiments, the apparatus includes a pixel array and a source driver configured to drive each column of the pixel array. In some embodiments, a setting method of charge sharing times includes grouping a plurality of pixels of a pixel array in a row direction to form a plurality of pixel groups. The setting method further includes setting a charge sharing time of each pixel group of the plurality of pixel groups according to a quantity of pixel groups in the plurality of pixel groups. A charge sharing time of a pixel group located closest to a source driver in the pixel array is greater than a charge sharing time of a pixel group located farthest from the source driver in the pixel array.

Setting method of charge sharing time and non-transitory computer-readable medium

A display device includes a display panel including data lines configured to receive an image signal, gate lines configured to receive a scan signal, and gate connection lines configured to transmit the scan signal to the gate lines; and a multi-chip film package including, on a film, a first gate integrated circuit (IC) configured to transmit a first scan signal to the gate connection lines through first gate output lines, a second gate IC configured to transmit a second scan signal to the gate connection lines through second gate output lines, and a source IC configured to transmit the image signal to the data lines through source output lines. Each of the first gate output lines is between two adjacent source output lines, and each of the second gate output lines is between two adjacent source output lines.

Display device including multi-chip film package having plurality of gate integrated circuits mounted thereon

A display apparatus includes a display panel including a plurality of horizontal lines each including a plurality of pixels, a timing controller configured to output a polarity control signal representing a polarity corresponding to each of the plurality of horizontal lines and having a value inverted by n horizontal line units, and a source driver configured to generate a timing pulse signal sequentially representing a data charging time of each of the plurality of horizontal lines and to output a data voltage, having a polarity corresponding to each of the plurality of horizontal lines, to the display panel on the basis of the timing pulse signal. When a value of the polarity control signal is inverted, the source driver generates the timing pulse signal including a data charging time corresponding to a count value obtained by counting a number of horizontal lines after a polarity is inverted.

Source driver controlling data charging times of horizontal lines of a display panel, display apparatus including the same, and operating method of the source driver

A display driving integrated circuit includes a common voltage buffer configured to provide a common voltage to a display panel and when a line outputting the common voltage and a gate line are short-circuited, apply a first current to the gate line or receive a second current from the gate line; a current generator configured to sum currents respectively corresponding to the first current and the second current and output an output current obtained by the summing; and a current detector configured to convert the output current into an output voltage and output a high or low signal based on a result of comparing the output voltage with a preset voltage.

Display driving integrated circuit and display device for short circuit detection

A display driving circuit includes a gamma generator configured to output, to nodes, gamma voltages having different voltage levels, and a selector configured to select one of the nodes to which the gamma voltages are output, and output a voltage of the selected one of the nodes. The display driving circuit further includes a voltage regulator configured to selectively input a first current to the selected one of the nodes and output a second current from the selected one of the nodes, based on the voltage of the selected one of the nodes, to adjust a voltage level of the voltage of the selected one of the nodes to a voltage level of a respective one of the gamma voltages that is output to the selected one of the nodes.

Display driving circuit for accelerating voltage output to data line

A source driver includes an interpolation amplifier configured to generate an interpolation voltage based on a received plurality of input voltages and output the interpolation voltage to a display panel; and an input selector configured to receive a first voltage and a second voltage having a different level from the first voltage, and configured to selectively provide at least one of the first and second voltages as the plurality of input voltages in response to some of the lower bits of pixel data. The interpolation amplifier includes four conductive differential input pairs configured to receive four input voltages from among the plurality of input voltages, respectively. Each of the first differential input pair and third differential input pair comprises a first type transistor. Each of the second differential input pair and fourth differential input pair comprises a second type transistor.

Interpolation amplifier and source driver including the same

Growing community of inventors

Hwaseong-si, South Korea

Yongjoo Song