Freescale Semiconductor,inc.

Motorola Corporation

Yongjoo Jeon

Choh-Fei Yeap

Srinivas Jallepalli

Geoffrey C-f Yeap

Jian Feng Chen

James David Burnett

Tab Allen Stephens

Michael D Turner

Paul Grudowski

Stanley Michael Filipiak

Toni D Van Gompel

Sangwoo Lim

Rana P Singh

An etch stop layer located over a plasma enhanced nitride (PEN) layer. Interlayer dielectric material is then formed over the etched stop layer. The etch stop layer is used as an etch stop for etching openings in the interlayer dielectric. In some embodiments, integrated circuits built with the PEN layer may include transistors with improved drive current at a given leakage current. Also, integrated circuits with the PEN layer may exhibit reduced parasitic capacitance.

Plasma enhanced nitride layer

Embodiments of the present invention relate to semiconductor structures having multiple gate dielectric structures. One embodiment forms semiconductor devices in multiple regions having different dielectric thicknesses where the interface between the gate dielectric and the semiconductor substrate is protected to result in an improved (e.g. less rough) interface. One embodiment includes forming a dielectric layer overlying a substrate, partially etching the dielectric layer in at least one of the multiple regions, and ashing the dielectric layer. The remaining portion of the dielectric layer (due to the partial etch) may then help protect the underlying substrate from damage during a subsequent preclean. Afterwards, in one embodiment, the gate dielectric layer is grown to achieve a target gate dielectric thickness in at least one of the regions. This may also help further densify the gate dielectric layer. Processing may then be continued to form semiconductor devices in each of the multiple regions.

Method for forming multiple gate oxide thickness utilizing ashing and cleaning

A process for forming an isolation trench in a wafer. The process includes depositing (e.g. by a directional deposition process) a first dielectric material in the trench and then depositing a second dielectric material (e.g. by a directional deposition process) over the first dielectric material in the trench. A third material is deposited in the trench on the second layer. The second material and the third material are selectively etchable with respect to each other. In one example, the first material has a lower dielectric constant than the second material.

Isolation trench

A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.

Integrated circuit device and method therefor

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Austin, TX, United States of America

Yongjoo Jeon