Sun Microsystems, Inc.

Oracle America, Inc.

Yonghee Im

Han Bin Kim

Frank C Chiu

Kyung T Lee

Yong Qin

A circuit for deterministic unparking of a strand of a microprocessor having multiple clock domains is described. The circuit includes a first flip-flop and a second flip-flop. Each flip-flop has a data input connected to receive a respective unpark signal, a clock signal at respective clock frequencies, and a respective enable signal. Each enable signal is generated by a respective logic block, each including a counter and each operating at a respective one of the clock frequencies. The second flip-flop has a data input connected to an output of the first flip-flop, and outputs an unpark signal that is used to unpark a strand of the microprocessor in a deterministic manner.

Deterministic test strand unparking

A method and apparatus for determining the size of a keeper transistor in a dynamic circuit is provided. A first portion of a dynamic circuit, comprising the keeper transistor, is analyzed to determine keeper current data that describes what size the keeper transistor would need to be to supply a specified amount of keeper current. A second portion of the dynamic circuit is analyzed, separate from the first portion, to determine an estimated amount of leakage current that passes through the PDN when the PDN is not actively discharging the dynamic node may be determined. The size for the keeper transistor that enables the keeper transistor, when activated, to produce an amount of keeper current that is substantially equal to the estimated amount of leakage current may be determined based on the analysis performed on the first and second portion.

Method and mechanism to determine keeper size

A method and apparatus for shifting a dynamic circuit, driven by a one-shot clock, to a pre-charge mode, during a power-off mode, is provided. Under certain conditions, a floating node may be present in a dynamic circuit. One approach to prevent floating nodes involves the generation of a new one-shot clock signal that is supplied to the last dynamic circuit in the series of dynamic circuits before the output flop ('the final dynamic circuit'). The new one-shot clock signal is driven to a logical low value when the power-off signal has a logical high value. Another approach to prevent floating nodes involves modifying the final dynamic circuit to include a structure that, when the power-off signal has a logical high value, drives the dynamic node to either a logical high value or a logical low value to prevent the dynamic node from becoming a floating node.

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Pleasanton, CA, United States of America

Yonghee Im