Samsung Electronics Co., Ltd.

Yongha Park

Ihor Vasyltsov

Youngnam Hwang

Jinmin Kim

Sangwan Nam

Hyunsuk Kim

Chaehoon Kim

Wooseok Chang

Jaehyung Ahn

Jaewon Yang

Hyunsik Park

Jinaeon Lee

Cheolkyoo Kim

Kilwhan Lee

A method of operating an accelerator includes receiving, from a central processing unit (CPU), commands for the accelerator and a peripheral device of the accelerator, processing the received commands according to a subject of performance of each of the commands, and transmitting a completion message indicating that performance of the commands is completed to the CPU after the performance of the commands is completed.

Accelerator, method of operating the accelerator, and device including the accelerator

An interconnect device may include one or more hardware-implemented modules configured to: receive a command from a processing core; perform, based on the received command, an operation including either one or both of an accumulation of sets of data stored in a memory and an aggregation of results processed by the processing core; and provide a result of the performing of the operation.

Interconnect device for selectively accumulating read data and aggregating processing results transferred between a processor core and memory

A ternary content addressable memory device (TCAM) may include: a cache memory storing a look-up table with respect to a calculation result of a plurality of functions; an approximation unit configured to generate mask bits; and a controller configured to obtain an approximation input value corresponding to an input key based on the mask bits and to retrieve an output value corresponding to the obtained approximation input value from the look-up table.

Ternary content addressable memory and operating method thereof

A method controls a memory device that includes a page buffer circuit comprising a plurality of page buffers each comprising at least one latch. The method includes generating by an internal voltage circuit at least one internal voltage among internal voltages used for an operation of the page buffer circuit, the internal voltage circuit providing the at least one internal voltage to the page buffer circuit; and providing to the page buffer circuit a control signal for forming an electrical connection between the internal voltage circuit and a first electrical node of a first page buffer unused for buffering in the page buffer circuit during a set operation for a first latch of a second page buffer.

Memory device for stabilizing internal voltage and method of stabilizing internal voltage of the same

A semiconductor memory device includes a memory cell array including first memory cells and second memory cell, and a peripheral circuit. When a first command, a first address, and first input data are received, the peripheral circuit reads first data from the first memory cells based on the first address in response to the first command, performs a first operation by using the first data and the first input data, and reads second data from the second memory cells by using a result of the first operation.

Semiconductor memory device for supporting operation of neural network and operating method of semiconductor memory device

Provided are a multimedia data processing system and a selective caching method. The selective caching method in the multimedia data processing system includes inserting cacheability indicator information into an address translation table descriptor undergoing memory allocation to a graphics resource when the graphics resource needs to be cached and selectively controlling whether or not to prefetch multimedia data of the graphics resource present in a main memory to a system level cache memory, with reference to cacheability indicator information during an address translation operation of a graphic processing unit (GPU). The inventive concept can be implemented in a wide variety of computer-based systems having a graphical output, such as cell phones, laptops, tablets, and personal computers, as only a few examples.

Method for caching GPU data and data processing system therefor

A method of processing multimedia data includes: separating a defined application kernel into a data patch kernel and a data processing kernel; requesting, by the data processing kernel, access to patch data of the multimedia data, from the data patch kernel; performing, by the data patch kernel, an operation that is independent of the request and preparing data for the data access based on the request; and performing, by the data processing kernel, an arithmetic operation on work items of the prepared data when the data has been prepared by the data patch kernel.

Multimedia data processing method in general purpose programmable computing device and data processing system according to the multimedia data processing method

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Seongnam-si, South Korea

Yongha Park