Lg Display Co., Ltd.

Yonggi Son

Woongki Min

Suhyuk Jang

Hongsung Song

Hong Sung Song

Chaeyoul Cho

Subyuk Jang

The exemplary embodiment relates to a liquid crystal display device. The liquid crystal display according to the exemplary embodiment includes: a liquid crystal display panel on which a plurality of data lines cross a plurality of gate lines, wherein each data line and each gate line is connected to a thin film transistor; a source drive IC supplying data voltages to the data lines; a gate drive IC supplying gate pulses to the gate lines; a system board equipped with a scaler that transmits data from the scaler through an interface that comprises 4-pair of data transmitting lines; and a control board equipped with a timing controller that receives the data through the interface and supplies the data to the source drive IC and controls the operating timing of the source drive IC and the gate drive IC.

Liquid crystal display

The exemplary embodiment relates to a liquid crystal display device. The liquid crystal display panel according to the exemplary embodiment includes: a liquid crystal display panel on which a plurality of data lines cross a plurality of gate lines; a source drive IC that supplies data voltages to the data lines; a gate drive IC that supplies gate pulses to the gate lines; a system board equipped with a scaler that transmits data from the scaler with a first interface specification; an interface board that receives the data according to the first interface specification, and transmitting the data with a second interface specification; and a control board equipped with a timing controller receiving the data in the second interface specification and supplying the data to the source drive IC, and controlling the operating timing of the source drive IC and the gate drive IC; wherein a number of the data transmitting lines required in the second interface specification is less than a number of data transmitting line required in the first interface specification.

A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a liquid crystal display panel including data lines and gate lines crossing each other and liquid crystal cells, a timing control signal generating unit, a data drive circuit supplying a data voltage to the data lines, and a gate drive circuit. The timing control signal generating unit generates a first gate timing control signal for controlling a scan direction of the liquid crystal display panel in a sequential direction and a second gate timing control signal for controlling the scan direction in a reverse sequential direction. The gate drive circuit supplies a gate pulse to the gate lines while a shift direction of the gate pulse changes in response to the first and second gate timing control signals.

Liquid crystal display with sequential and reverse sequential scan direction to improve display quality by preventing stains caused by polarization and accumulation of ions, and driving methods thereof

A liquid crystal display and a method for driving the same are disclosed. The liquid crystal display includes a timing controller generating a polarity control signal. A logic inverting period of the polarity control signal during frame periods ranging from an Nth frame period among M frame periods to 2 to 4 frame periods following the Nth frame period is longer than a logic inverting period of the polarity control signal in the other frame periods, where N is an integer equal to or larger than 4 and M is larger than N. The liquid crystal cells in one frame period of the M frame periods are charged to the data voltage whose a polarity is opposite to a polarity of the data voltage in a previous frame period of one frame period.

Liquid crystal display to increase display quality by preventing DC image sticking, flicker and stains

A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing signal multiplying circuit generating a first timing signal and a second timing signal whose frequency is higher than a frequency of the first timing signal, a frame counter detecting a multiplied frame period to be driven at the frequency of the second timing signal, a data processing circuit allowing a frequency of digital data output during the multiplied frame period to be higher than a frequency of the digital data output during a frame period except the multiplied frame period, a timing control signal generating circuit generating a polarity control signal for controlling polarities of the digital data, and a polarity control signal inverting circuit that increases a frequency of the polarity control signal during the multiplied frame period to generate an inverse polarity control signal.

Liquid crystal display having function of suppressing stain and method of driving the same

A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing signal multiplying circuit multiplying a frequency of a timing signal, a timing control signal generating circuit generating a polarity control signal based on the multiplied timing signal, a polarity control signal inverting circuit that inverts the polarity control signal in response to an inverse periodic signal, that is inverted every constant time interval, to generate an inverse polarity control signal, and a data drive circuit that respectively converts digital video data and digital black data into a video data voltage and a black gray level voltage, inverts polarities of the video data voltage and the black gray level voltage in response to the inverse polarity control signal, and supplies the video data voltage and the black gray level voltage to data lines.

Liquid crystal display and method of driving the same

A liquid crystal display and a method of driving the same are disclosed. A timing controller of the liquid crystal display controls a polarity control signal to have a different phase in each frame and allows liquid crystal cells to be divided into a first liquid crystal cell group charged to a data voltage of a same polarity during two frame periods and a second liquid crystal cell group charged during a current frame period to the data voltage with a polarity opposite a polarity of the data voltage charged during a previous frame period. The liquid crystal cells belonging to the first liquid crystal cell group are successively charged to the data voltage of the same polarity during three or more frame periods at intervals of a predetermined time equal to or longer than two frame periods.

Liquid crystal display and driving method thereof

A liquid crystal display device and a driving method thereof are provided which can increase a display grade by removing a DC residual image. The liquid crystal display device comprises: a liquid crystal display panel for displaying gray levels by a potential difference between a common electrode for applying a common voltage and pixel electrodes for applying data voltages; a common voltage regulating circuit for generating a variable common voltage which is longitudinally symmetrical with respect to a DC common voltage of a predetermined level and whose voltage level is stepwisely varied at predetermined intervals; and a black gamma reference voltage regulating circuit for adding the variable common voltage to an offset voltage set as a gamma reference voltage of a black gray level to generate a variable gamma reference voltage varying with respect to the gamma reference voltage of the black gray level, the variable gamma reference voltage of the black gray level being varied in synchronization with the variable common voltage.

Liquid crystal display device and driving method thereof

A liquid crystal display (LCD) capable of improving display quality and a method of driving the same are provided. The LCD comprises an LCD panel including a plurality of data lines and gate lines and liquid crystal cells arranged in a matrix at crossings of the gate lines and the data lines, a driving circuit for supplying a data voltage to the data lines and for supplying a scan pulse to the gate lines, a timing controller for generating a gate start pulse for indicating a start horizontal line in which scanning starts in a one frame period where one screen is displayed, a control clock generator for counting the number of frames using the gate start pulse and for generating a control clock whenever an accumulated count value becomes a multiple of a predetermined value, and a common voltage generating circuit for generating control data of a specific bit based on the control clock and for generating a common voltage whose level varies in stages per predetermined interval using the control data to supply the common voltage to the LCD panel.

A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a liquid crystal display panel, a data drive circuit, a gate drive circuit, and a timing controller. The data drive circuit generates a pre-charge data voltage during pre-charge time and generates a real-charge voltage to be displayed on the liquid crystal display panel during real-charge time. The gate drive circuit supplies a first gate pulse synchronized with the pre-charge data voltage to the gate lines during the pre-charge time while shifting a gate pulse in a downward direction and an upward direction depending on an up/down signal, and then supplies a second gate pulse synchronized with the real-charge data voltage to the gate lines from a falling edge of the first gate pulse at intervals equal to or longer than scanning time of 1 line during the real-charge time.

A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a data drive circuit that supplies a data voltage, whose a polarity is periodically inverted, to the data lines, a gate drive circuit, and a timing controller. The gate drive circuit sequentially supplies a first gate pulse synchronized with a first data voltage to gate lines, and sequentially supplies a second gate pulse synchronized with a second data voltage having a polarity opposite a polarity of the first data voltage, to the gate lines. The timing controller generates a pre-gate start pulse for controlling an output of the first gate pulse during a blank period, and then generates a real gate start pulse for controlling an output of the second gate pulse during an initial period of a frame period following the blank period.

Growing community of inventors

Milyang-si, South Korea

Yonggi Son