Spansion Llc.

Yonggang Wu

Nian Niles Yang

Guowei Wang

Tien-Chun Yang

Aaron Lee

Boon-Aik Ang

Sachit Chandra

Fan Wan Lai

Wei Daisy Cai

David Aoyagi

A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.

Flash memory programming power reduction

Commonly, read times of a memory line are slowed due to voltage overshoot and/or voltage undershoot. To eliminate these problems, a control component can manage voltage while a leakage component manages timing of voltage. This allows for a line pre-charge that produces increase read times. The control component can implement as a variable resistor that modifies value to compensate for temperature. The leakage component can include a capacitor configuration that allows voltage to pass.

Circuit pre-charge to sense a memory line

A method of forming a capacitor for use as a charge pump with flash memory, comprising: (a) concurrently forming polysilicon gates on a semiconductor body in a core region and a polysilicon middle capacitor plate in a peripheral region, (b) forming a first dielectric layer over the polysilicon gates and the middle capacitor plate, (c) planarizing the first dielectric layer to expose a top portion of the polysilicon gates and a top portion of the middle capacitor plate, (d) forming a second dielectric layer over the top portion of the middle capacitor layer, (e) concurrently forming patterning a second polysilicon layer in the core region and a third capacitor plate in the periphery region and (f) connecting the third capacitor plate to the source/drain well.

Capacitor structure used for flash memory

One embodiment of the invention relates to a method for accessing a memory cell. In this method, at least one bit of the memory cell is erased. After erasing the at least one bit, a soft program operation is performed to bias the memory cell thereby improving the reliability of data stored in the memory cell. Other methods and systems are also disclosed.

Methods and systems for memory devices

A fast reference circuit having active feedback includes a bias supply circuit and a variable divider circuit connected by an active feedback path to the bias supply circuit, and a comparator circuit connected to the variable divider circuit, the bias supply circuit, and a reference node of the variable divider circuit. In one embodiment, a start-up circuit initially discharges a potential at the bias supply and comparator circuits, then initializes a reference voltage at the reference node at about zero volts to improve repeatability. In one embodiment, the variable voltage divider comprises an impendence that is trimmed based on a sheet resistance of a process used to fabricate the fast reference circuit, and further comprises a variable reference current circuit coupled to the impedance and configured to generate a current having a value based on a desired reference voltage and to conduct the current through the impedance, thereby generating the reference voltage associated therewith. The comparator circuit is configured to compare the bias supply voltage to the reference voltage, and drive the bias supply and the variable divider circuit in response to the comparison, thereby quickly stabilizing the reference voltage.

Method to provide a higher reference voltage at a lower power supply in flash memory devices

A semiconductor memory device () selectably connectable to an external high voltage power supply () is provided. The semiconductor memory device () includes a switch (), a detector () and a timing device (). The switch () is connected to external voltage supply signals and selectably couples the external voltage supply signals to memory cells () of the semiconductor memory device () for memory operations thereof. The external voltage supply signals including a high voltage signal () provided from the external high voltage power supply () and an operational voltage signal Vcc (). The detector () is connected to the external voltage supply signals for generating a timer activation signal () in response to detecting an operational voltage power-on period. The timing device () signals the switch () to decouple the high voltage signal () and the operational voltage signal () from the memory cells () in response to the timer activation signal () and to recouple the high voltage signal () and the operational voltage signal () to the memory cells () a time delay interval thereafter. The time delay interval is determined in response to the high voltage signal ().

Flash memory device with external high voltage supply

A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells () of a semiconductor memory device (). A high voltage generator () during program or erase operations provides a continuous high voltage level () on selected word lines () and maintains a continuous high voltage level supply to a bit line decoder () which sequentially provides the high voltage level () to a first portion of bit lines () and discharges () those bit lines () before providing the high voltage level to a second portion (). For additional improvements to program operations, the high voltage generator () decouples high voltages provided to the word lines () and the bit lines () by providing a current flow control device () therebetween and provides a boosting voltage at a time () to overcome a voltage level drop () resulting from a capacitor load associated with selected bit lines () and/or the bit line decoder () precharges () a second portion of the bit lines () while providing a high voltage level to a first portion to program () a first portion of memory cells (). For improvements to read operations, whether dynamic reference cells () are blank is determined by providing non-identically regulated high voltage levels from a first voltage source () to the dynamic reference cells () and from a second voltage source () to static reference cells () and, if the dynamic reference cells () are not blank, reads selected memory cells () by providing identically regulated high voltage levels to the selected memory cells (), the dynamic reference cells () and the static reference cells ().

Method and apparatus for high voltage operation for a high performance semiconductor memory device

Manners for transferring information within a flash memory device across a memory array are described. A controller retrieves information from a storage unit and then a decoder decodes the information. The information is set across a series of bitlines through a pass gate to a second controller. The bitlines are both associated with the storage unit as well as bitlines associated with other storage units. A series of transistors is associated with each bitline. Different transistors are active based on if the bitlines are associated with the currently used storage unit.

Transfer of non-associated information on flash memory devices

A voltage regulator comprises resistor elements that mitigate variations in a program voltage (VPROG). In particular, the resistors allow copies of the voltage regulator to be fabricated more consistently across a semiconductor substrate. As such, variations in respective program voltages applied to different bitlines of a memory arrangement are mitigated. This mitigates yield loss as more devices perform as desired, thus necessitating fewer discards.

Drain voltage regulator

A method and apparatus are provided for improved noise reduction from switching on and off drain pumps () in a high voltage generator. The drain pumps () are divided into groups () and activation of the groups () of drain pumps () is staggered (). In addition, when drain pumps are switched on and off for power conservation or to maintain a steady state high voltage level, the groups () of drain pumps () are switched on and off in response to various predetermined high voltage levels (), with different voltage levels for different groups () of drain pumps ().

Method and apparatus for drain pump operation

A voltage regulator may include an operational-amplifier section, a capacitor connected to an output of the operational-amplifier section, and a switch configured to connect the capacitor to a voltage supply. The switch is configured to charge the capacitor before activating the operational-amplifier section. The capacitor is configured to store charge to supplement current being supplied from the operational-amplifier section. The voltage regulator may be used to supply power to non-volatile memory cells.

Voltage regulator with less overshoot and faster settling time

A non-volatile memory cell array, such as a Flash NOR array, is programmed by applying voltages to bit lines that connect to memory cells in the memory cell array. A first bit line corresponding to a first memory cell in the memory array may be turned on to perform a first programming operation for the first memory cell and second bit line corresponding to a second memory cell in the memory array may be turned on to perform a second programming operation that is configured to complete after the first programming operation. The turning on/off of the first and second bit lines may be overlapped to share charge between the first and second bit lines. This overlapping can reduce wasted power and decrease programming pulse overshoot problems.

Growing community of inventors

Santa Clara, CA, United States of America

Yonggang Wu