Shanghai Zhaoxin Semiconductor Co., Ltd.

Yongfeng Song

Shuai Zhang

Jiangbo Wang

Yankui Niu

Jinglong Liu

Jintao Wang

Qunchao Feng

Weilin Wang

Yang Shi

Xiaoliang Kang

Xuemin Zhang

Xiaoliang Ji

Yixing Mei

An operation method of a sleep mode of an electronic device includes the following steps. A first sub-module of a first module sends a sleep command to a second sub-module of the first module and a third sub-module and a fourth sub-module of a second module, wherein the first sub-module includes first and second modes, the second sub-module includes third and fourth nodes, the third sub-module includes fifth and sixth nodes, and the fourth sub-module includes seventh and eighth nodes. The second sub-module, the third sub-module and fourth sub-module execute a sleep sequence in sequence to enter a sleep mode according to the sleep command. The first node sends the sleep command to the second node to execute the sleep sequence to enter the sleep mode. The first node sends the sleep command to the first node to execute the sleep sequence to enter the sleep mode.

Electronic device and operation method of sleep mode thereof

Packet routing within a multi-chip processing system is shown. A first chip has a first interconnect bus, and a first microprocessor coupled to the first interconnect bus. The first interconnect bus has a first routing register. When the first microprocessor operates the first chip as a source node to output a packet to be transferred to a destination node, routing information indicating a routing path from the source node to the destination node is written into the first routing register and then loaded from the first routing register to a header of the packet. While being transferred within the multi-chip processing system from the source node to the destination node, the packet is guided along the routing path indicated in the routing information carried in the header of the packet.

Multi-chip processing system and method for adding routing path information into headers of packets

A booting technology for a multi-die and multi-core computing platform is shown. A storage device stores numberfirmware code and numberfirmware code. A master die is coupled to the storage device through a bus and accesses the numberfirmware code from the storage device through the bus. A first slave die is also coupled to the storage device through the bus. However, instead of accessing the storage device for the numberfirmware code, the first slave die monitors the bus and retrieves the numberfirmware code, accessed by the master die, from the bus. The master die further accesses the numberfirmware code from the storage device through the bus. The master die executes the numberfirmware code to operate the master die and the first slave die to boot the system and start up the platform.

Multi-die and multi-core computing platform and booting method for the same

A multi-die and multi-core computing platform in which multiple dies share the same storage device for firmware code storage is shown. After a slave die loads #1 firmware code from the storage device through a bus, the right to use the bus is released by the slave die and the slave die outputs a #0 enable signal to a master die. According to the #0 enable signal, the master die gains the right to use the bus. Through the bus, the master die loads #0 firmware code from the storage device. The slave die executes the #1 firmware code and the master die executes the #0 firmware code to initialize a link between the master and slave dies.

Multi-die and multi-core computing platform and booting method therefor

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Beijing, China

Yongfeng Song