Samsung Electronics Co., Ltd.

Yongchul Oh

Hyun-Woo Chung

Hui-Jung Kim

Kang-Uk Kim

Hyun-gi Kim

Yoosang Hwang

Daeik Kim

Jiyoung Kim

Hyeongsun Hong

Sungkwan Choi

Dong-Hyun Kim

Keunnam Kim

Dongsoo Woo

Semyeong Jang

Young-Seung Cho

SungMin Kim

Donggun Park

Gyoyoung Jin

Yonggyu Choi

Kichul Nam

Eunjung Yoon

A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

Methods of operating and forming semiconductor devices including dual-gate electrode structures

A semiconductor device includes line patterns disposed on a substrate, the line patterns extending in a first direction and being parallel to one another. The semiconductor device includes conductive patterns spaced apart from each other in the first direction between an adjacent pair of the line patterns. The semiconductor device includes insulating fences electrically isolating the conductive patterns from each other and having chamfered corners. The semiconductor device includes insulating patterns filling gaps between side surfaces of the line patterns and the chamfered corners of the insulating fences.

Semiconductor device and method of fabricating the same

A semiconductor device includes a semiconductor substrate including first trenches defining outer sidewalls of a pair of active pillars and a second trench defining opposing inner sidewalls of the pair of active pillars. The second trench may have a bottom surface located at a higher level than bottom surface of the first trench. Auxiliary conductive lines may be disposed in the first trenches to cover and cross the outer sidewalls of the pair of active pillars. A pair of main conductive lines may be disposed in a pair of recessed regions that are laterally recessed from lower portions of the inner sidewalls of the active pillars into the pair of active pillars. A common impurity region may be disposed in the semiconductor substrate under the second trench. Upper impurity regions may be disposed in upper portions of the active pillars.

Semiconductor devices and methods for manufacturing the same

Semiconductor devices with vertical channel transistors, the devices including semiconductor patterns disposed on a substrate, first gate patterns disposed between the semiconductor patterns on the substrate, a second gate pattern spaced apart from the first gate patterns by the semiconductor patterns, and conductive lines crossing the first gate patterns. The second gate pattern includes a first portion extending parallel to the first gate patterns and a second portion extending parallel to the conductive lines.

Semiconductor devices with vertical channel transistors

Methods of fabricating semiconductor devices may include forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches extend in parallel. A gate dielectric layer is formed on upper inner sidewalls of the first trenches, and a gate conductive layer filling the first trenches is formed on the substrate including the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars. Semiconductor devices may also be provided.

Semiconductor devices including vertical channel transistors and methods of fabricating the same

Provided is a semiconductor device having a vertical channel transistor and method of fabricating the same. The semiconductor device includes first and second field effect transistors, wherein a channel region of the first field effect transistor serves as source/drain electrodes of the second field effect transistor, and a channel region of the second field effect transistor serves as source/drain electrodes of the first field effect transistor.

Semiconductor device with vertical channel transistor

Provided are a vertical channel transistor and a method for fabricating a vertical channel transistor. The method includes forming an active layer on a substrate, forming a plurality of vertical channels on the active layer, forming a plurality of isolated gate electrodes to surround sidewalls of the plurality of vertical channels, forming a buried bitline to extend along the active layer between the plurality of vertical channels, forming a plug-in between the plurality of vertical channels to connect the plurality of isolated gate electrodes and forming a wordline on a location where the plug-in and the plurality of isolated gate electrodes are connected.

Vertical channel transistors and methods for fabricating vertical channel transistors

Semiconductor memory devices and methods of forming the same are provided, the semiconductor memory devices include a first and a second buried gate respectively disposed on both inner sidewalls of a groove formed in an active portion and a device isolation pattern. The first and second buried gates are controlled independently from each other.

Semiconductor memory devices and methods of forming the same

An integrated circuit device includes a device isolation pattern on a semiconductor substrate to define an active area therein. The active area includes a doped region therein. A conductive pattern extends on the active area and electrically contacts the doped region. The conductive pattern has a lower resistivity than the doped region. The conductive pattern may be disposed in a recessed region having a bottom surface lower than a top surface of the active area. A channel pillar electrically contacts to the doped region and extends therefrom in a direction away from the substrate. A conductive gate electrode is disposed on a sidewall of the channel pillar, and a gate dielectric layer is disposed between the gate electrode and the sidewall of the channel pillar.

Integrated circuit devices including low-resistivity conductive patterns in recessed regions

Methods of fabricating vertical channel transistors may include forming an active region on a substrate, patterning the active region to form vertical channels at sides of the active region, forming a buried bit line in the active region between the vertical channels, and forming a word line facing a side of the vertical channel.

Methods of fabricating vertical channel transistors

A method of fabricating a vertical channel transistor includes: forming a line type active pattern on a substrate so as to extend in a first horizontal direction; forming a vertical channel isolating the active pattern in a second horizontal direction intersecting the first horizontal direction and extending vertically on the substrate; forming a buried bit line extending in the first horizontal direction on the substrate; and forming a word line extending in the second horizontal direction along at least one side surface of the vertical channel.

Method of fabricating vertical channel transistor

In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region, a portion of the semiconductor substrate in the cell region and in the peripheral circuit region including an isolation region defining an active region, a portion of the active region protruding above an upper surface of the isolation region to define at least two active channels, a gate dielectric layer formed over the active region of the semiconductor substrate including the at least two protruding active channels, a gate electrode formed over the gate dielectric layer and the isolation region of the semiconductor substrate, and a source/drain region formed in the active region of the semiconductor substrate on either side of the gate electrode.

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Suwon-si, South Korea

Yongchul Oh