Samsung Electronics Co., Ltd.

Yongbum Kwon

Unbyoung Kang

A method of manufacturing a semiconductor chip is provided. The method includes: forming a plurality of bonding pads on a semiconductor wafer, sequentially forming an insulating layer and a polishing stop film on the semiconductor wafer to cover the plurality of bonding pads, the insulating layer and the polishing stop film having a plurality of convex portions corresponding to upper portions of the plurality of bonding pads, polishing the plurality of convex portions using the polishing stop film to expose upper surfaces of the plurality of bonding pads, and removing the polishing stop film.

Manufacturing method of semiconductor chip

A method of manufacturing a semiconductor package includes bonding first the and second structures, such that a first bonding structure is directly bonded to a second bonding structure. The forming of the first structure includes; forming a blocking layer on a metallic material layer including a first portion covering a concaved portion of the metallic material layer and a second portion covering a non-concaved portion of the metallic material layer, performing a first planarization process to remove the second portion of the blocking layer while the first portion of the blocking layer remains, performing a second planarization process to remove the non-concaved portion of the metallic material layer and expose the barrier layer on the insulating layer, performing a wet etching process to remove the barrier layer on the insulating layer and the blocking layer to form the first bonding pad including the barrier layer in the opening and the metallic material layer and forming a recessed portion below an upper surface of the metallic material layer on the barrier layer while removing the barrier layer on the insulating layer.

Semiconductor package and method of manufacturing same

Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a bit line provided to cross an active region of a substrate, isolation patterns provided on the substrate to face each other in a direction parallel to the bit line, a storage node contact provided between the isolation patterns to be in contact with a source/drain region provided in an upper portion of the active region, and a spacer provided between the bit line and the storage node contact. Here, the isolation patterns may include a material having an etch selectivity with respect to the spacer.

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Yongin-si, South Korea

Yongbum Kwon