Huawei Technologies Co., Limited

Yongbing Huang

Jun Xu

Mingyu Chen

Yuan Ruan

Zehan Cui

Licheng Chen

Yao Liu

Yuangang Wang

Shihai Xiao

Tao Huang

Rui Bang He

Tingqiu Yuan

Kun Zhang

Tongtong Cao

Qinfen Hao

Mingyang Chen

Shuncheng Pan

Chengda Wu

Rui He

In a data reading operation, a first terminal in a distributed storage system obtains a first data identifier, which is a unique identifier of first data in the distributed storage system. The first terminal determines, based on the first data identifier, whether first data is local data. When the first data is not local data, the first terminal obtains a first identifier that uniquely identifies the first data in the distributed storage system. The first terminal obtains, based on the first identifier, a second identifier corresponding to the first data and associated with content of the first data. The first terminal obtains, based on the second identifier, a read address that indicates that the first data is stored at a second terminal in the distributed storage system. The first terminal then retrieves the first data from the second terminal.

Data reading method and terminal

This application discloses a database data compression method and a storage device, which are applicable to lossless compression of a relational database. The method includes parsing a first data block to obtain m pieces of first data, where the first data is row/column data, and the first data block is obtained based on database data. Then, the method includes classifying the m pieces of first data according to a machine learning algorithm or a deep learning algorithm, to obtain n classification categories, and transforming first data in each classification category to obtain target data. The method further includes compressing the target data to obtain compressed data. In this application, data in different rows/columns is classified according to the machine/deep learning algorithm, and then the row/column data belonging to the same classification category is transformed and compressed.

Database data compression method and storage device

A cache management method, a cache controller, and a computer system are provided. In the method, the cache controller obtains an operation instruction; when a destination address in the operation instruction hits no cache line cache line in a cache of the computer system, and the cache includes no idle cache line, the cache controller selects a to-be-replaced cache line from a replacement set, where the replacement set includes at least two cache lines; and the cache controller eliminates the to-be-replaced cache line from the cache, and stores, in the cache, a cache line obtained from the destination address. According to the cache management method, system overheads of cache line replacement can be reduced, and cache line replacement efficiency can be improved.

Cache management method, cache controller, and computer system

A dynamic random access memory (DRAM) refresh method in which a to-be-refreshed area in a refresh block is specified in a refresh instruction is provided to refresh a specified location of a DRAM storage array. A memory controller sends a refresh instruction to a DRAM refresh apparatus. The refresh instruction includes an identifier of a to-be-refreshed block and refresh information indicating a to-be-refreshed area. The DRAM refresh apparatus generates addresses of to-be-refreshed bank rows in the to-be-refreshed block according to the identifier and the refresh information, and refresh locations corresponding to the addresses of the bank rows in the to-be-refreshed block. Therefore, a DRAM refresh time is shortened, refresh power consumption is reduced, a refresh operation is more flexible, and system resource consumption is reduced while data integrity is ensured.

DRAM refresh method, apparatus, and system

A memory management method and a device, where the method includes: receiving a memory access request, where the memory access request carries a virtual address; determining a page fault type of the virtual address if finding, in a translation lookaside buffer TLB and a memory, no page table entry corresponding to the virtual address; allocating a corresponding page to the virtual address if the page fault type of the virtual address is a blank-page-caused page fault, where the blank-page-caused page fault means that no corresponding page is allocated to the virtual address; and updating the page table entry corresponding to the virtual address to the memory and the TLB. The memory manager does not generate a page fault when a blank-page-caused page fault occurs, but allocates a corresponding page to the virtual address. Therefore, a quantity of occurrences of the page fault is reduced, thereby improving memory management efficiency.

Memory management and device

An optical switch control method and an apparatus are disclosed, to reduce impact on access performance by time overheads of optical link switching. The method includes: receiving an optical link establishment request sent by a computation node; determining whether the first optical link that needs to be established conflicts with the existing optical link; and if the first optical link that needs to be established conflicts with the existing optical link, determining whether to allow establishment of the first optical link, and establishing the first optical link if the establishment of the first optical link is allowed; or establishing the first optical link if the first optical link that needs to be established does not conflict with the existing optical link.

Optical switch control method, and apparatus

A method for refreshing a dynamic random access memory DRAM and a computer system are provided. When an address of a refresh unit in a DRAM and refresh information of the refresh unit are acquired, the address of the refresh unit and the refresh information of the refresh unit are encapsulated as a DRAM access request, where the refresh unit is storage space on which one time of refresh is performed in the DRAM, and the refresh information of the refresh unit includes a refresh cycle of the refresh unit. Then, the address and the refresh information of the refresh unit are written into refresh data space using the DRAM access request, where the refresh data space is storage space that is preset in the DRAM and that is used for storing an address of at least one refresh unit and refresh information of the at least one refresh unit.

Method for refreshing dynamic random access memory and a computer system

A method for reducing power consumption of a memory system and a memory controller are provided. The method for reducing power consumption of a memory system includes: determining whether a dynamic random access memory DRAM memory module with a low access frequency exists in a memory system; when a DRAM memory module with a low access frequency exists, transfer, according to a size of a working set in the memory system, page data that does not belong to the working set to a non-volatile memory NVM memory module, where the page data that does not belong to the working set is page data that does not need to be accessed when a process runs within preset time.

Method for reducing power consumption of memory system, and memory controller

A memory access processing method is based on memory chip interconnection, a memory chip, and a system, which relate to the field of electronic devices, and can shorten a time delay in processing a memory access request and improve a utilization rate of system bandwidth. The method of the present disclosure includes receiving, by a first memory chip, a memory access request; and if the first memory chip is not a target memory chip corresponding to the memory access request, sending, according to a preconfigured routing rule, the memory access request to a next memory chip connected with the first memory chip, until the target memory chip corresponding to the memory access request is determined. Embodiments of the present disclosure are mainly used in a process of processing a memory access request.

Memory access processing method, memory chip, and system based on memory chip interconnection

A message-based memory access apparatus and an access method thereof are disclosed, The message-based memory access apparatus includes: a message-based command bus, configured to transmit a message-based memory access instruction generated by the CPU to instruct a memory system to perform a corresponding operation; a message-based memory controller, configured to package a CPU request into a message packet and sent the packet to a storage module, and parse a message packet returned by the storage module and return data to the CPU; a message channel, configured to transmit a request message packet and a response message packet; and the storage module, including a buffer scheduler, and configured to receive the request packet from the message-based memory controller and process the corresponding request.

Message-based memory access apparatus and access method thereof

The present invention discloses a memory access method, a buffer scheduler, and a memory module, which can support multiple application scenarios without changing the memory module or a memory chip. The method includes: receiving an operation request message for memory access data, where the operation request message includes tag information of the memory access data, operation information of the memory access data, and a memory address of the memory access data; and performing, according to at least one of the tag information of the memory access data, a memory address of the memory access data, and the operation information of the memory access data, an operation on the tag of the memory access data and/or the memory access data stored in the memory module. The present invention is applicable to the computer field.

Growing community of inventors

Beijing, China

Yongbing Huang