Xiamen Tianma Micro-electronics Co., Ltd.

Shanghai Tianma Micro-electronics Co., Ltd.

Xiamen Tianma Display Technology Co., Ltd.

Tianma Micro-electronics Co., Ltd.

Wuhan Tianma Micro-electronics Co., Ltd

Hubei Yangtze Industrial Innovation Center of Advanced Display Co., Ltd.

Tongji University

Tianma Japan, Ltd.

Yong Yuan

Qingjun Lai

Yihua Zhu

Ping An

Zhaokeng Cao

Jieliang Li

Qijun Yao

Zaiwen Zhu

Feng Lu

Jujian Fu

Shui He

Wanming Huang

Qitai Ji

Yuheng Zhang

Quanpeng Yu

Yingteng Zhai

Guofeng Zhang

Nana Xiong

Linshan Guo

Jinjin Yang

Yaqi Kuang

Heeyol Lee

Hong Lin

Hongming Chen

Xiang Cai

Xingyao Zhou

Zhongshou Huang

Chao Wang

Kazushige Takechi

Liang Liu

Chen Liu

Conghua Ma

Ying Liu

Huiping Chai

Junqiang Wang

Xianxiang Zhang

Shaolong Ma

Yungang Sun

Xiaoye Li

Jun Tanaka

Shucheng Ge

Meng Lai

Chen Zhong

Wenze Shan

Meng Cui

Chengxu Li

Xiangyuan Li

Xiaoyun Wang

Chunmei He

Jiaolong Zhang

Kenji Sera

Yongxiang Lin

Danping Wei

Feng Xie

Kerong Wu

Xupeng Yao

Ruyi Sheng

A display panel and a display device are provided. The display panel includes a pixel circuit including a driving transistor and a preset module, a light-emitting element, a driving circuit, and a gating module. A first terminal of the preset module is connected to the driving transistor, a second terminal of the preset module is connected to a preset signal terminal or the driving transistor, a control terminal of the preset module is connected to a control signal line, and the control signal line is configured to receive a control signal. The driving circuit is configured to provide the control signal for the control signal line. The gating module is connected between the control terminal of the preset module and the driving circuit. The gating module is connected to a gating signal line, and the gating signal line is configured to receive a gating signal.

Display panel and display device

A display panel includes: first and second display areas; first and second pixel circuits connected to light-emitting elements in the first and second display areas, respectively; and first pixel units and second pixel units, each first pixel unit comprising a first pixel circuit and a light-emitting element connected to the first pixel circuit, and each second pixel unit comprising a second pixel circuit and a light-emitting element connected to the second pixel circuit, wherein each first pixel unit includes the light-emitting element emitting light of a first color, each second pixel unit includes the light-emitting element emitting light of a second color, the first color is different from the second color, each first pixel unit is configured to receive a first power supply signal and a second power supply signal, and each second pixel unit is configured to receive a third power supply signal and a fourth power supply signal.

Display panel, integrated chip component and display device

A display panel and a display device are provided. The display panel includes a pixel circuit including a driving transistor and a preset module, a light-emitting element, and a gating module. A first terminal of the preset module is connected to the driving transistor, a second terminal of the preset module is connected to a preset signal terminal or the driving transistor, a control terminal of the preset module is connected to a control signal line, and the control signal line is configured to receive a control signal. The gating module is connected to a gating signal line, and the gating signal line is configured to receive a gating signal. In at least a portion of an operation process of the display panel, a pulse change frequency of the gating signal is F, and a pulse change frequency of the control signal is Fc, and F≠Fc.

A display panel includes a driver circuit including shift registers with N stages and being cascade with each other, where N≥2, and each shift register includes a first control portion and a second control portion. The first control portion is configured to control a first output signal, where the first output signal of an i-th stage of shift register is an input signal of a j-th stage of shift register, and 1≤i≤N, 1≤j≤N. The second control portion is configured to receive at least the first output signal and a frequency control signal and control a second output signal. In a case where the first output signal is an effective pulse and a time period of the effective pulse is within a time period of an effective pulse of the frequency control signal, the second output signal is the effective pulse.

Provided are an array substrate and a manufacturing method of an array substrate and a display panel and device. The array substrate includes a pixel circuit. The pixel circuit includes a first transistor and a second transistor, the first transistor includes a first active layer, the second transistor includes a second active layer, and the first active layer and the second active layer both include silicon. The array substrate further includes a first-type inorganic layer and a second-type inorganic layer and a first via hole. The first via hole is located above the first active layer and at least penetrates through the second-type inorganic layer. Concentration of hydrogen ions in the first active layer is less than concentration of hydrogen ions in the second active layer.

Array substrate and manufacturing method thereof including via hole to facilitate dehydrogenation, display panel, and display device

A display panel and a display device are provided. The display panel includes a substrate, signal lines located on the substrate, and a plurality of light-emitting elements each located on a side of one of the signal lines facing away from the substrate. Each light-emitting element includes a first electrode, a light-emitting layer, and a second electrode that are stacked sequentially. Each signal line includes at least one overlapping portion overlapping the light-emitting layer of one of the light-emitting elements in a direction perpendicular to the display panel. An angle θ between an extending direction of a part of the at least one overlapping portion and a pixel column direction in a display region that satisfies: 0°<θ<90°, or an angle θ between an extending direction of a tangent of a part of the at least one overlapping portion and a pixel column direction in a display area that satisfies: 0°<θ<90°.

Display panel and display device with reduced dispersion

A display panel includes a front surface, a back surface, a display region, a binding region, a first flexible substrate, and a thin-film transistor. The display region is arranged on the front surface and configured to display a picture. The binding region is arranged on the back surface and at least partially overlaps with the display region. The thin-film transistor layer is arranged on a side of the first flexible substrate close to the front surface of the display panel. The first flexible substrate is arranged between the thin-film transistor layer and the binding region.

A display panel includes at least one driving circuit and at least one pixel circuit. A driving circuit of the at least one driving circuit provides a driving signal for a pixel circuit of the at least one pixel circuit. The driving circuit includes N-level shift registers cascaded with each other. N is greater than or equal to two. The pixel circuit provides a display signal for a display unit of the display panel. A shift register of the N-level shift registers includes at least one first transistor. The at least one first transistor includes at least one first active layer, and an active layer with a largest area among the at least one first active layer is a first preset active layer. The pixel circuit includes at least one second transistor. The at least one second transistor includes at least one second active layer.

A display panel includes a base substrate, a first transistor and a second transistor. The first transistor and the second transistor are formed on the base substrate. The first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes silicon. The second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer includes an oxide semiconductor. A length of a channel region of the first transistor is L1. Along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1. The first transistor further includes a third gate electrode. Along the direction perpendicular to the base substrate, a distance between the third gate electrode and the first active layer is D3, and D1<D3.

Provided are a display panel and a preparation method thereof, and a display device. The display panel includes a base substrate; a first transistor, a second transistor, a third transistor; and a pixel circuit supplying a drive current to a display element, and a driver circuit supplying a drive signal to the pixel circuit; where the driver circuit includes the first transistor, and the pixel circuit includes the second transistor and the third transistor; and the subthreshold swing of the first transistor is SS, and the subthreshold swing of the second transistor is SS, where SS<SS

Display panel and preparation method thereof, and display device

A display panel includes a base substrate, a third transistor and a fourth transistor. The third transistor and the fourth transistor are formed on the base substrate. The third transistor includes a sixth gate electrode, a third active layer, a third source electrode, and a third drain electrode. The third active layer includes an oxide semiconductor. The fourth transistor includes an eighth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode. The fourth active layer includes another oxide semiconductor. Along a direction perpendicular to the base substrate, a distance between the sixth gate electrode and the third active layer is D. A channel region of the third transistor defined by the sixth gate electrode is a sixth channel region. A length of the sixth channel region is L. A sixth area S=L×D

Provided are a display panel, an integrated chip, and a display device. The display panel includes a first display region, a second display region, and a pixel circuit. The pixel circuit includes a first pixel circuit and a second pixel circuit, where the first pixel circuit is connected to a light-emitting element in the first display region, and the second pixel circuit is connected to a light-emitting element in the second display region. The pixel circuit includes a drive transistor and a first presetting module, and a terminal of the first presetting module is connected to the drive transistor, where a control terminal of a first presetting module in the first pixel circuit is configured to receive a first control signal, and a control terminal of a first presetting module in the second pixel circuit is configured to receive a second control signal.

Display panel, integrated chip, and display device

Provided are a display panel, an integrated chip, and a display device. The display panel includes a first display region, a second display region, and a pixel circuit. The pixel circuit includes a first pixel circuit and a second pixel circuit, where the first pixel circuit is connected to a light-emitting element in the first display region, and the second pixel circuit is connected to a light-emitting element in the second display region. In at least one stage of a working process of the display panel, the light-emitting element in the first display region works in a first brightness mode, the light-emitting element in the second display region works in a second brightness mode, brightness in the first brightness mode is L1, and brightness in the second brightness mode is L2, where L1≠L2.

A display panel includes a base substrate, a first transistor, and a second transistor. The first transistor and the second transistor are formed on the base substrate. The first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes silicon. The second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer includes oxide semiconductor. A length of a channel region of the first transistor is L1. Along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1. A length of a channel region of the second transistor is L2. Along the direction perpendicular to the base substrate, a distance between the second gate electrode and the second active layer is D2.

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Shanghai, China

Yong Yuan