Electronics and Telecommunications Research Institute

Yong Youn Kim

Sang Man Moh

Jae Sung Lee

Kyoung Ran Park

Youngwoo Kim

Young Woo Kim

Myung-Joon Kim

Myung Joon Kim

Sung Nam Kim

Kee-Wook Rim

Kee Wook Rim

A device for effectively and economically receiving a packet by eliminating temporary memory and a memory controller. The apparatus includes an inspection logic circuit for inspecting data units as soon as they arrive in order to find an error included in the packet and generating control signals according to a result of inspecting a data unit; a multiplexer for receiving data units and distributing the received data units as soon as the data units have arrived; and FIFO memories for receiving the data unit, storing the data unit in a corresponding one of FIFO memories and either deleting or completing storing data units according to the control signals from the inspection logic circuit. The present invention can reduce manufacturing cost of the device by eliminating a temporary memory and a memory controller for the temporary memory and can also reduce processing time.

Apparatus for receiving data packet eliminating the need of a temporary memory and memory controller and method thereof

In a first-in first-out memory circuit using a standard cell library memory, a memory block includes N number of memories (N&#x3e;1). A read pointer designates read addresses of the N number of memories. A write pointer designates write addresses of the N number of memories. A memory controller selects one from the N number of memories based on the read/write addresses, generates n number of read/write clock signals by demultiplying a clock signal by n (n=N, n&#x3e;1) and sends the n number of read/write clock signals having a 1/n cycle difference to the N number of memories thereby inputting/outputting data.

First-in first-out memory circuit and method for executing same

Disclosed herein is an interrupt redirection apparatus and method for inter-processor communication. The apparatus includes a plurality of ARM processors, a vectored interrupt controller, an interrupt command register, an interrupt data register for designating the contents of each interrupt, an interrupt signal generation unit, and a bus interface unit used for providing read and write accesses of both the interrupt command register and the interrupt data register. The vectored interrupt controller for receiving interrupts generated by hardware for performing a specific function under the control of each ARM processor and interrupts generated by peripheral hardware, and transferring each interrupt as each interrupt request signal to an ARM processor designated as a master processor. The interrupt command register designates targets and kinds of each interrupt to perform a function for receiving an interrupt redirection command and activating an interrupt request signal. The interrupt signal generation unit reads the contents and activates an interrupt request signal.

Method and apparatus for interrupt redirection for arm processors

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Daejeon, South Korea

Yong Youn Kim