Applied Materials, Inc.

Beijing Wodong Tianjun Information Technology Co., Ltd.

Yong Yang

Srinivas Gandikota

Yixiong Yang

Jacqueline S Wrench

Steven C H Hung

Seshadri Ganguli

Mandyam Sriram

Benjamin Colombeau

Joung Joo Lee

Annamalai Lakshmanan

Chi Zhang

Myungsun Kim

Feihu Wang

Luping Li

Xiaochuan Fan

Yun Xiao

Shiliang Diao

Lingfei Wu

Xincheng Wang

A method of forming a contact structure in a semiconductor device having a feature includes forming a barrier layer in the feature, wherein the barrier layer is TiN; and forming a metal layer in the feature and over the barrier layer, wherein the metal layer is at least one of aluminum (Al), ruthenium (Ru), or molybdenum (Mo).

Methods and apparatus for seam reduction or elimination

A method for recommending a product, includes: providing product information having a product description, a main image, and a plurality of alternate images; for each alternate image: performing saliency segmentation to obtain a segment and a background, defining a segment bounding box enclosing the segment, extracting image feature from the segment bounding box, extracting textual feature from the product description, extracting main image feature from the main image, matching the image feature of the segment bounding box to the textual feature and the main image feature, and determining the alternate image as a qualified alternate image if the image feature of the segment bounding box matches the textual feature and the main image feature; and when a number of the qualified alternate image equals to or is greater than a threshold number, recommending the product to customers.

System and method for validating product photography

A method of forming a gate stack structure includes forming a dipole metal layer on a high-κ gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-κ gate dielectric layer.

Threshold voltage modulation for gate-all-around FET architecture

Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiments comprise NbN as a PMOS work function material at a thickness in a range of greater than or equal to 5 Å to less than or equal to 50 Å. The PMOS work function material comprising NbN has an effective work function of greater than or equal to 4.75 eV. Some embodiments comprise HfOas a high-κ metal oxide layer. Some embodiments provide improved PMOS bandedge performance evidenced by improved flatband voltage. Some embodiments exclude transition metal niobium nitride materials as work function materials.

PMOS high-k metal gates

Methods for DRAM device with a buried word line are described. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

Low resistivity DRAM buried word line stack

A method of forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-κ dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-κ dielectric cap layer, and removing the sacrificial silicon cap layer.

Treatments to enhance material structures

Growing community of inventors

Boston, MA, United States of America

Yong Yang