Samsung Electronics Co., Ltd.

Yong-Weon Jeon

Il-Kwon Chang

Kyung-Wol Kim

Ji-Woon Jung

Jang-Jin Nam

Do-Kyung Kim

Jong-Hoon Hong

Jan-Jin Nam

Ji-woon Jung

Dong-Hoon Baek

Beop-Hee Kim

Jo-Hyun Ko

Jang-Sub Lee

Il-kwon Chang

A source driver of a display panel includes a channel state signal generator, first switches, and second switches. The channel state signal generator generates first and second channel state signals that are each activated for a respective time period depending on adjustable state length data. The first switches are opened for uncoupling channel output signals from source lines of the display panel when the first channel state signal is activated. The second switches are closed for coupling together the source lines of the display panel for charge sharing when the second channel state signal is activated.

Flexible control of charge share in display panel

A device for controlling the level of a transmission signal according to the channel loading is provided. The device may include a plurality of semiconductor devices and a controller to control the plurality of semiconductor devices. The controller may control the level of a signal to be transmitted to each of the plurality of semiconductor devices according to the channel loading on each semiconductor device.

Device for adjusting transmission signal level based on channel loading

Embodiments of the invention provide a digital-to-analog converter (DAC) that is configured to process upper data bits, a control data bit, and a lower data bit using two decoders and a control logic. The resulting DAC provides high resolution output using a minimum circuit area. Embodiments of the invention also provide a sample and hold circuit for a DAC that reduces the effects of parasitic capacitance at the input of an operational amplifier (OP-AMP).

Digital to analog converter with minimum area and source driver having the same

A display device includes a first set of data buses coupled between a timing controller and a first line driver. In addition, the display device also includes a second set of at least one data bus coupled between the first line driver and a second line driver. The second set has a less number of at least one data bus than the first set. Thus, data signals are transmitted to the line drivers of the display panel from the timing controller with minimized wiring for reduced power consumption and electromagnetic interference.

Routing signals to drivers of display device with minimized wiring

Embodiments of methods and apparatus for receiving data are disclosed. More particularly, methods of receiving a current mode signal, which can improve a signal to noise ratio (SNR) according to a change in a power supply voltage, and current mode comparators and semiconductor devices that use the methods are provided. A method of receiving a current mode signal includes receiving a reference current signal and a data current signal through a channel and generating a sensing voltage based on a difference between the reference current signal and the data current signal, varying a transconductance to reduce an input resistance of the current mode comparator in inverse proportion to an increase in a power supply voltage supplied to the current mode comparator, and converting the sensing voltage into a CMOS level output signal using the current mode comparator.

Semiconductor devices for receiving a current mode signal and methods of operating the same

For generating source line voltages in a display device, gray scale data is received at a source driver for a first sub-pixel of a pixel. The source driver generates a first source line voltage for the first sub-pixel and a second source line voltage for a second sub-pixel from the gray scale data of the first sub-pixel. Thus, data transfer rate and/or data buses are minimized for in turn minimizing power consumption and EMI (electromagnetic interference).

Driving multiple sub-pixels from single gray scale data

A digital/analog converting driver and a digital/analog converting method, in which the digital/analog converting driver converts digital data having M+N (M and N are integers) bits into an analog voltage and includes a first converting unit, a second converting unit, and an analog voltage outputting unit. The first converting unit converts successive M bits of the digital data into a first voltage. The second converting unit converts successive N bits of the digital data into a second voltage. The analog voltage outputting unit adds the first voltage and the second voltage and outputs the added voltage as the analog voltage. The output range of the first voltage is different from that of the second voltage.

Digital/analog converting driver and method

Provided is a current-mode semiconductor integrated circuit device that operates in a voltage mode during a test mode. The current-mode semiconductor integrated circuit device includes a first transmitting converter, a first receiving converter, a second transmitting converter, and a second receiving converter. During the test mode, one of a first signal path and a second signal path is selected according to the location of the chip. In the first signal path, the first transmitting converter, the first receiving converter, and the second transmitting converter operate. In the second signal path, the second transmitting converter, the second receiving converter, and the first transmitting converter operate. Each of the first and second transmitting converters receives a test voltage signal and converts it into a current signal. Each of the first and second receiving converters generates a reference voltage signal, compares it with the test voltage signal, and outputs the comparing result.

Current-mode semiconductor integrated circuit device operating in voltage mode during test mode

A current mode comparator for a semiconductor device is disclosed. The current mode comparator may include a logic circuit coupled to a voltage sensing node, a first cascode coupled to the voltage sensing node and a first power node, and a second cascode coupled to the voltage sensing node and a second power node. The logic circuit may convert a voltage of the voltage sensing node to an output signal.

Cascode-type current mode comparator and receiver, and semiconductor device having the same

A digital to analog converter (DAC) converting digital data into a corresponding analog voltage is disclosed. The digital data includes upper bit data and lower bit data and the DAC includes; a first resistor circuit dividing first and second reference voltages to output a plurality of first division voltages, a first decoder selecting one of the first division voltages in response to the upper bit data, a second resistor circuit dividing third and fourth reference voltages to output a plurality of second division voltages, a second decoder selecting one of the second division voltages in response to the lower bit data, and a sample and hold circuit including a first capacitor and a second capacitor, and outputting the analog voltage in response to an output voltage from the first decoder and an output voltage from the second decoder, wherein the sample and hold circuit samples the output voltage of the first decoder during a sample mode, and adds the output voltages of the first and second decoders through the first and second capacitors to output a combined voltage during a hold mode.

Digital to analog converter and source driver

A pseudo differential current mode receiver includes a regulated cascode buffer for buffering a received data current to generate a buffered data current with cascode-reduced input impedance and cascode-increased output impedance. In addition, a signal converter generates an output signal indicating a difference between the buffered data current and a reference current. The reference current may also be received and buffered by a regulated cascode buffer with cascode-reduced input impedance and cascode-increased output impedance.

Pseudo differential current mode receiver

Provided are a receiver and a transceiver for multi-level current-mode signaling, which together may reduce the number of bus lines and increase a data bandwidth. A transmitter transmits one reference current and a multi-level data current. On the basis of the reference current signal received from the transmitter, a receiver generates plural internal reference currents for determining the multi-level data current received from the transmitter, and converting the received multi-level data current into a data voltage having the desired level corresponding to the data that was transmitted.

Receiver and transceiver for multi-level current-mode signaling

A regulated cascode amplifier includes a main cascode amplifier and a feed-back amplifier. The main cascode amplifier has an input transistor coupled in a stack with an output transistor at an input control node. The feed-back amplifier including a plurality of transistors with gates of the transistors being coupled together to the input control node and with drains of the transistors being coupled together at a gate of the output transistor. The transistors of the feed-back amplifier are biased from connections to the main cascode amplifier for smaller chip area.

Growing community of inventors

Suwon-si, South Korea

Yong-Weon Jeon