International Business Machines Corporation

Cameron International Corporation

Chartered Semiconductor Manufacturing Ltd (corporation)

Yong Wee Lee

Haining S Yang

Haw Keat Lim

Victor W C Chan

Sanjay Menon

Victor Chan

Eng Hing Lim

Boon Hao Hee

Ping Cheng Lai

Sufian Bin Mohamed Arip

Kim Siang Ong

Srivathsan Sudershan Vuruputoor

Boon Keng Tay

Albert Christian

A seal monitoring system includes at least one sensor configured to couple to an outer surface of a housing and to output a sensor signal indicative of deformation of the housing. The housing is configured to receive an insert within an internal cavity of the housing, and an engageable seal is configured to selectively establish a seal between the insert and the housing. The seal monitoring system also includes a controller communicatively coupled to the at least one sensor. The controller includes a memory and a processor, the controller is configured to determine a degree of engagement of the engageable seal based on the deformation of the housing. Additionally or alternatively, the controller is configured to determine a fluid pressure within the housing based on the deformation of the housing.

Seal monitoring system

Smart wellhead assemblies with sensors for detecting positions of components within the bores of the wellhead assemblies are provided. In some instances, the sensors can be used to detect one or more of landing, locking, or concentricity of hangers, packoffs, or other internal wellhead components within bores. In one example, a method of installing a hanger within a wellhead includes lowering the hanger within the wellhead and using one or more sensors to detect when the hanger is at a target location. The method can also include activating a locking mechanism of the hanger and using the one or more sensors to detect when the locking mechanism has secured the hanger within the wellhead. Additional systems, devices, and methods are also disclosed.

Smart wellhead

A system includes a running tool having a tool body configured to couple to a hanger assembly, a first sleeve disposed around the tool body and configured to move in an axial direction with respect to the tool body, a torque sleeve disposed around the tool body and configured to move in the axial direction as a result of movement of the first sleeve in the axial direction, where the torque sleeve has a first torque transfer interface configured to interlock with a second torque transfer interface of the hanger assembly to enable torque transfer from the running tool to the hanger assembly, and a second sleeve configured to couple to the first sleeve, where the second sleeve is configured to move to engage a lock member of the hanger assembly and to move the lock member between a locked position and an unlocked position.

Running tool for tubing hanger

A method is provided for fabricating a semiconductor device structure. In such method a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), each of the NFET and the PFET having a conduction channel disposed in a single-crystal semiconductor region of a substrate. A stressed film having a compressive stress at a first magnitude can be formed to overlie the PFET and the NFET. Desirably, a mask is formed to cover the PFET while exposing the NFET, after which, desirably, a portion of the stressed film overlying the NFET is subjected to ion implantation, while the mask protects another portion of the stressed film overlying the PFET from the ion implantation. The substrate can then be annealed, whereby, desirably, the compressive stress of the implanted portion of the stressed film is much reduced from the first magnitude by the annealing. In such way, the implanted portion of the stressed film overlying the NFET desirably imparts one of a much reduced magnitude compressive stress, a zero stress and a tensile stress to the conduction channel of the NFET. Another portion of the stressed film can continue to impart the compressive stress at the first magnitude to the conduction channel of the PFET.

Method of applying stresses to PFET and NFET transistor channels for improved performance

Methods of fabricating a semiconductor device including a dual-hybrid liner in which an underlying silicide layer is protected from photoresist stripping chemicals by using a hard mask as a pattern during etching, rather than using a photoresist. The hard mask prevents exposure of a silicide layer to photoresist stripping chemicals and provides very good lateral dimension control such that the two nitride liners are well aligned.

Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals

A semiconductor device structure is provided which includes a first semiconductor device; a second semiconductor device; and a unitary stressed film disposed over both the first and second semiconductor devices. The stressed film has a first portion overlying the first semiconductor device, the first portion imparting a first magnitude compressive stress to a conduction channel of the first semiconductor device, the stressed film further having a second portion overlying the second semiconductor device, the second portion not imparting the first magnitude compressive stress to a conduction channel of the second semiconductor device, the second portion including an ion concentration not present in the second portion such that the second portion imparts one of a compressive stress having a magnitude much lower than the first magnitude, zero stress, and a tensile stress to the conduction channel of the second semiconductor device.

Growing community of inventors

Singapore, Singapore

Yong Wee Lee