Integrated Device Technology, Inc.

Huawei Technologies Co., Limited

Tyco Electronics (shanghai) Co., Ltd.

Other

Chinese Academy of Sciences

Fluke Corporation

Cisco Technology, Inc.

Emc IP Holding Company LLC

Freescale Semiconductor,inc.

Alcatel Lucent

Nxp Usa, Inc.

Lsi Corporation

Baidu USA LLC

Spreadtrum Communications (shanghai) Co., Ltd.

Cummins Power Generation Ip, Inc.

Yong Wang

Shaohua Yang

Jian Li

Liang Zhang

Xin Liu

Yu Chen

Jianfeng Wang

Jian Ouyang

Quanzhong Gao

Shuhui Chen

Fan Wang

Wei Luo

Yu Zhang

Tao Zeng

Yuhang Zhao

Jianhua Li

Xiaoming Shi

Cheng Ye

Xiaoqun Chen

Yinhong Yang

Jinquan Yan

Mingguang Zheng

Pengzhan Zhang

Chunfu Zhou

Guoxing Gu

Wei Wang

Yan Chen

Hao Tang

Hui Wang

Wei Cao

Zhe Liu

Yang Han

Wei Zhu Chen

Yi Bu Li

Jun Hui Liu

Dan Liu

Zheng Wang

Yong Yang

Guohua Zhou

Jing Wang

Yi He

Yunfu Luo

Wei Shi

Shoujun Wang

Feng Wang

Xiang Xu

Chengde Wu

Feng Guo

Tao Yu

Zhitang Song

Xiaoxu Kang

Xianliang Chen

Feng Shi

Liwen Zhang

Xichun Gao

Si Yuan Zhang

Shiyuan Li

Jinjin Ni

Hefei Zhu

Ning Li

Bin Xiong

Zhongyuan Chang

Xiaojun Zheng

Shuai Chen

Yulin Li

Hua He

He Sun

Qi Zuo

Jueping Wang

Zhenhua Zhang

Maoyi Lei

Xiaozhang Gong

Gang Yan

Changjun Wang

Hui Xiang

Jiahu Wu

Xuefeng Ji

Zhibiao Zhao

Feng Rao

Qingshu Chen

Lingfeng Lin

Mo Chen

Shengyuan Zhang

Zongbin Li

Jun Xie

Fangwei Zheng

Kathy Xia Ke

Tenghao Li

Xia Wei

Zhuo Chen

Honghui Ge

Dongyan Chu

Chongbin Fan

Xun Fan

Guoli Zhang

Chunting Li

Lingwei Kong

The disclosure provides a multi-mode frequency division circuit including a frequency division factor processor, a frequency divider, and a logic operator. The frequency division factor processor receives the frequency division factor, decomposes the frequency division factor to obtain a first sub-frequency division factor and a second sub-frequency division factor, and outputs the first sub-frequency division factor or the second sub-frequency division factor according to a frequency division clock signal. The divider performs frequency division on the clock signal based on the first sub-frequency division factor or the second sub-frequency division factor to generate the frequency division clock signal. The logic operator sequentially samples the frequency division clock signal according to the rising edge and falling edge of the clock signal to generate a first signal and a second signal, and the logic operator generates an output clock signal according to the first signal, the second signal, and an indication signal.

Multi-mode frequency division circuit

Provided are a glycosyltransferase UGT76G1 mutant, an isolated polynucleotide, a carrier, a production method, and a composition and a kit for the glycosylation of substrates. Further provided are a method for increasing the catalytic activity of the glycosyltransferase UGT76G1 mutant, and a method for promoting the glycosylation of flavone compounds and the use thereof. The glycosyltransferase UGT76G1 mutant is subjected to mutations at positions corresponding to positions 87, 199, 204 or 379 of SEQ ID NO: 1, and significantly improves the transformation activity of substrates of the flavone compounds.

Preparation of glycosyltransferase UGT76G1 mutant and use thereof

Fish biscuit

Provided are a baicalein- and scutellarein-synthesizing microorganism, a preparation method for same, and applications thereof. By modifying a heterologous metabolic pathway of a host cell per a genetic engineering method, acquired is an engineered strain providing a high yield of baicalein and scutellarein. Also provided is a process for utilizing the engineered strain to produce baicalein and scutellarein.

Baicalein- and scutellarein-synthesizing microorganism, preparation method and applications thereof

Rawhide treat for dogs

The present disclosure provides example wavelength selective switch (WSS), wavefront control element, and integrated liquid crystal on silicon (LCoS). One example WSS includes an input port fiber array, a demultiplexing/multiplexing grating group, an output port fiber array, and a beam deflection component group including two beam deflection components and at least one wavefront control element located between the demultiplexing/multiplexing grating group and the beam deflection component group or integrated with the LCoS. At least one beam deflection component is a LCoS. The input port fiber array receives multi-wavelength optical signals. The demultiplexing/multiplexing grating group demultiplexes and outputs the multi-wavelength optical signals. The beam deflection component group deflects the multi-wavelength optical signals to the demultiplexing/multiplexing grating group. The demultiplexing/multiplexing grating group multiplexes the multi-wavelength optical signals to the output port fiber array. The wavefront control element and the LCoS jointly modulate optical signals transmitted through N*M wavelength channels.

Wavelength selective switch WSS

Presented herein are embodiments of an improved asymmetric quantization, which may generally be referred to as improved asymmetric quantization (IAQ) embodiments. IAQ embodiments combine the benefits of conventional asymmetric quantization and symmetric quantization but also provide additional computation efficiencies. Embodiments of IAQ adopt an asymmetric range of the weights of a neural network layer, so they circumvent the limitation of symmetric range of symmetric quantization. Moreover, the inference process of a neural network quantized by an IAQ embodiment is much faster than that of the neural network quantized by conventional asymmetric quantization by quantizing an offset value of each layer.

Asymmetric quantization for compression and for acceleration of inference for neural networks

Provided is a fused tri-cyclic compound as PDE3/PDE4 dual inhibitor, and a use thereof in the preparation of drugs for PDE3/PDE4 associated diseases, particularly in medicinal functions such as chronic obstructive pulmonary disease (COPD). Provided are specifically a compound of formula (I) and a pharmaceutically acceptable salt thereof.

Fused tri-cyclic compound as PDE3/PDE4 dual inhibitor

A plug connector includes a metal housing, an insulation body received in the metal housing, the insulation body having an insertion slot, a signal terminal disposed in the insulation body, a power terminal disposed in the insulation body, and a metal sheet. The metal sheet is disposed in the insertion slot. The signal terminal and the power terminal are separated from each other by the metal sheet.

Plug connector, receptacle connector and connector assembly

Tumbler toy for pets

A locking device adapted to lock a shell to an installation body includes a thread connection member extending through a connecting hole in the shell and engaging a threaded hole in the installation body, a sealing ring sleeved on the thread connection member and adapted to be pressed on an installation surface of the shell to seal the connecting hole of the shell, and a gasket sleeved on the thread connection member and adapted to be pressed between the thread connection member and the sealing ring to prevent the thread connection member from being loosened. The gasket has a pair of stopping arms. An angle defined between the stopping arms is greater than 0 degrees and less than 180 degrees. A pair of top ends of the stopping arms are adapted to simultaneously abut against an outer wall of the shell to prevent the gasket from rotating with the thread connection member.

Locking device and connector

The invention relates to a crystalline form of lamotrigine hydrate, a method for preparing the same and a composition comprising the same, and in particular, to a lamotrigine hydrate form A, a method for preparing the lamotrigine hydrate form A and a composition comprising the lamotrigine hydrate form A.

Crystalline form of lamotrigine hydrate, method for preparing the same and composition comprising the same

The present invention relates to processor testing technology, specifically relating to a method for automatically testing a processor, the method comprising: S, carrying out test preparation; S, setting an operation voltage and a clock frequency of a processor to be tested; S, carrying out load testing at the current operation voltage and clock frequency; S, determining whether the processor is normal during current load testing; if yes, then turning to step S; if no, then raising the current operation voltage by a first growth value and returning to step S; and S, recording an operation voltage, subject to load testing, which corresponds to the current clock frequency as a test result and determining whether the current clock frequency reaches an upper limit; if yes, then ending the operation; if no, then raising the current clock frequency by a second growth value and returning to step S. The described method is capable of implementing the automatic testing of processors and rapidly and effectively obtaining operation voltages corresponding to clock frequencies when the processors are operating normally, and is thus suitable for a plurality of platforms.

Method for automatically testing processor

Methods, apparatuses, devices, and storage media for performing a processing task are provided. A portion of portions of the processing task can include a group of operations that are to be performed at a processing unit of processing units. The group of operations can include operations of a first type and operations of a second type. In the method, a first queue for performing the operations of the first type and a second queue for performing the operations of the second type can be built, respectively. Based on a definition of the processing task, a dependency relationship between a group of operations to be performed at the processing unit and a group of operations to be performed at other processing units in the plurality of processing units can be obtained. Operations in the first queue and operations in the second queue can be performed respectively based on the dependency relationship.

Method, apparatus, device, and storage medium for performing processing task

Embodiments of this application relate to the field of wireless communications technologies, and provide an access method, a switch method, and an apparatus. The access method includes: receiving, by a terminal, a system message via a downlink carrier, where the system message includes information used to indicate a frequency channel number of a second uplink carrier; and initiating, by the terminal, random access via the second uplink carrier, where a frequency channel number of the downlink carrier belongs to a first frequency band, and a frequency channel number of the second uplink carrier belongs to a second frequency band.

Communication method and apparatus

Growing community of inventors

Shanghai, China

Yong Wang