Samsung Electronics Co., Ltd.

Gwangju Institute of Science and Technology

Kwangju Institute of Science and Technology

Edith Cowan University

Ytel Photonics Inc.

Yong-Tak Lee

Yong-hwa Park

Yong-chul Cho

Byung-hoon Na

Chang-young Park

Gun-wu Ju

Hyeong-Geun An

Kyu-Mann Lee

Hee-ju Chio

Chang-soo Park

Kyung-Hyun Kim

Jang-woo You

Young Min Song

Yong-Hwa Park

Jung Hye Chae

Myoung-Sik Han

Ki-Soo Chang

Alameh Kamal

Bong-Kyu Jeong

Kwang-mo Park

Sung Joon Jang

Hee-ju Choi

Yong-Chul Cho

Chang-Young Park

Jang-Woo You

Kwang-Mo Park

Byung-Hoon Na

Gun-Wu Ju

The present invention relates to a silicon DBR structure-integrated light device, and a preparation method thereof, and more specifically, to a silicon DBR structure-integrated light device or vertical cavity light emitting diode, and a preparation method thereof, enabling preparation by a small number of layers and capable of reducing process time and costs due to a large contrast in refractive index of a silicon DBR structure formed by depositing silicon in a slanted or vertical manner.

Silicon DBR structure-integrated light element, and preparation method

An optical device is provided including an active layer having two outer barriers and a coupled quantum well between the two outer barriers. The coupled quantum well includes a first quantum well layer, a second quantum well layer, a third quantum well layer, a first coupling barrier between the first quantum well layer and the second quantum well layer, and a second coupling barrier between the second quantum well layer and the third quantum well layer. A thickness of the first quantum well layer and a thickness of the third quantum well layer are each different from a thickness of the second quantum well layer. Also, an energy level of the first quantum well layer and an energy level of the third quantum well layer are each different from an energy level of the second quantum well layer.

Optical device including three-coupled quantum well structure having multi-energy level

Provided is an optical device which includes an active layer which includes at least two outer barriers and at least one coupled quantum well, each of the at least one coupled quantum well is sandwiched between the at least two outer barriers. Each of the at least one coupled quantum well includes at least three quantum well layers and at least two coupling barriers interposed between the at least three quantum layers. The at least two coupling barriers have a potential energy which is higher than a ground level and is lower than energy levels of the at least two outer barriers.

Optical device including three coupled quantum well structure

A transmissive light modulator including a first reflection layer; a first active layer, arranged on the first reflection layer and including a plurality of quantum well layers and a plurality of barrier layers; a second reflection layer arranged on the first active layer; a second active layer, arranged on the second reflection layer and including a plurality of quantum well layers and a plurality of barrier layers; and a third reflection layer arranged on the second active layer, wherein the first reflection layer and the third reflection layer are each doped with a first type dopant, and the second reflection layer is doped with a second type dopant, which is electrically opposite to the first type dopant.

Transmissive image modulator including stacked diode structure having multi absorption modes

Optical modulator having wide bandwidth based on Fabry-Perot resonant reflection is disclosed. The optical modulator includes: a bottom Distributed Bragg Reflector (DBR) layer; a top DBR layer including at least one layer, and a modified layer; and an active layer disposed between bottom and top DBR layers, wherein the at least one layer includes at least one pair of a first refractive index layer having a first refractive index and a second refractive index layer having a second refractive index, the modified layer includes at least one pair of a third refractive index layer having a third refractive index and a fourth refractive index layer having a fourth refractive index, the third and the fourth refractive indexes being different, and at least one of the third and the fourth refractive index layers has a second optical thickness that is not &#x3bb;/4 or that is not an odd multiple thereof.

Optical modulator

An optical image modulator and a method of manufacturing the same. The optical image modulator includes a substrate, an N electrode contact layer formed on the substrate, a lower distributed Bragg reflection (DBR) layer, a quantum well layer, an upper DBR layer, and a P electrode contact layer sequentially stacked on the N electrode contact layer, a P electrode formed on the P electrode contact layer, and an N electrode formed on the N electrode contact layer. The N electrode is a frame that surrounds the lower DBR layer.

Optical image modulator and method of manufacturing the same

Provided are a method of fabricating a microlens using selective etching of a compound semi-conductor and a method of fabricating a photoelectric device having the microlens. The formation of the microlens includes patterning a compound semiconductor layer and removing a lateral surface of the compound semiconductor layer to form a roughly hemispheric lens. The lateral surface of the compound semiconductor layer is removed by a digital alloy method. In particular, the lateral surface of the compound semiconductor layer is removed by a wet etching process.

Method for fabricating micro-lens and micro-lens integrated optoelectronic devices using selective etch of compound semiconductor

A ferroelectric memory device and a method of fabricating the same are disclosed. Four interlayer dielectric layers are stacked on cell array and peripheral circuit regions on a semiconductor substrate. A gate contact pad and a source/drain contact pad are connected to a gate electrode and a source/drain of the peripheral circuit transistor through the first interlayer dielectric layer. A gate contact plug and a source/drain contact plug are respectively connected to the gate contact pad and the source/drain contact pad through the second interlayer dielectric layer. First via holes expose the gate contact plug and the source contact plug through the third interlayer dielectric layer. A first interconnection extends between the third and fourth interlayer dielectric layers, covering the sidewalls of the first via holes and connected to at least one of the gate contact plug and the source/drain contact plug.

Method of fabricating a ferromagnetic memory device

The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern is performed.

Ferroelectric memory device and method of forming the same

The present invention is about phased array antenna using gain switched multimode Fabry-Perot laser diode (FP-LD) and high-dispersion fiber. More particularly, the invention deals with techniques that allow compact and low-cost system implementation for phased array antenna adopting optical control and also allows continuous time delay for each antenna in the array to induce phase difference.

Phased array antenna using gain switched multimode fabry-perot laser diode and high-dispersion-fiber

Ferroelectric memory device and method of fabricating the same

A method of fabricating a semiconductor device having a capacitor with a high dielectric constant layer includes a groove for an alignment key is formed together with a contact hole on a substrate; a conductive layer of tungsten is formed to fill the contact hole and cover the inner surface of the groove; a capping layer for use as an oxygen barrier is stacked on the conductive layer of tungsten; a planarization process is performed using CMP to leave the capping layer and the conductive layer of tungsten covering the inner surface of the groove to form a contact plug filling the contact hole; a capacitor bottom electrode layer is stacked to contact the top surface of the contact plug; a high dielectric constant layer is stacked on the bottom electrode layer; and an oxidation treatment is performed at a high temperature to crystallize the high dielectric constant layer.

Method of forming memory device having capacitor including layer of high dielectric constant

Growing community of inventors

Gwangju, South Korea

Yong-Tak Lee