Samsung Electronics Co., Ltd.

Yong-Tae Yim

Sung-Kue Jo

Yun-ho Choi

Sung-Kyu Jo

Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.

Memory system providing wear-leveling by allocating memory blocks among groups

Memory system and wear-leveling method thereof based on erasures and error correction data

Disclosed are program and read methods for a nonvolatile memory system, including determining to program first data in which one of fast and normal modes; providing the first data with an error code generated by a multi-bit ECC engine, in the fast mode, and generating second data; programming the second data in a cell array by a program voltage having a second start level higher than a first start level; and reading the second data from the cell array, the second data being output after processed by the multi-bit ECC engine that detects and corrects an error from the second data.

Nonvolatile memory device, system, and method providing fast program and read operations

An error correction circuit and method for reducing a miscorrection probability and a semiconductor memory device including the circuit are provided. The error correction circuit includes an error check and correction (ECC) encoder and an ECC decoder. The ECC encoder generates syndrome data enabling h-bit error correction based on information data and a generator polynomial, where 'h' is 2 or an integer greater than 2. The ECC decoder may operate in a single mode for detecting an error position with respect to a maximum of (h&#x2212;j) bits in the information data based on encoded data including the information and the syndrome data, where 'j' is 1 or an integer greater than 1. Alternatively, the ECC decoder may operate in a first operation mode for detecting an error position with respect to a maximum of &#x201c;h&#x201d; bits in the information data or in a second operation mode for detecting an error position with respect to a maximum of (h&#x2212;j) bits in the information data based on encoded data including the information and the syndrome data. Accordingly, the miscorrection probability is reduced, and therefore, data reliability is increased.

Error correction circuit and method for reducing miscorrection probability and semiconductor memory device including the circuit

An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficient calculator, and a determiner. The partial syndrome generator calculates at least two partial syndromes using coded data. The first error position detector calculates a first error position using a part of the partial syndromes. The coefficient calculator calculates coefficients of an error position equation using the at least two partial syndromes. The determiner determines an error type based on the coefficients. The second error position detector optionally calculates a second error position based on the error type. The semiconductor memory device includes the error correction circuit, an error checking and correcting (ECC) encoder generating syndrome data based on information data and generating the coded data by combining the syndrome data with information data, and a memory core storing the coded data. Multi-bit ECC performance is maintained and ECC for a predetermined (1 or 2) or less number of error bits is quickly performed.

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Suwon-si, South Korea

Yong-Tae Yim