Samsung Electronics Co., Ltd.

Volentine, Whitt & Francos, Pllc

Yong-Sung Cho

Se-heon Baek

Jung-ho Song

Il-Han Park

Moo-sung Kim

Jong-Min Baek

Bong-Kil Jung

Sang-Yong Yoon

Jung-Yun Yun

Seung-You Baek

Nam-hee Lee

Youn-ho Hong

A memory device includes a memory cell array including a plurality of memory cells on which a programming loop is executed a plurality of times; a voltage generator configured to apply a verifying voltage to the memory cells, for verifying at least one programming state of the memory cells; and a voltage controller configured to control the voltage generator to change a level of the verifying voltage as a program loop count increases, based on temperature information about a temperature inside or outside the memory device.

Memory device and memory system

In some example embodiments, a program pulse is applied to a resistive memory cell and a plurality of post pulses are applied to the resistive memory cell at a time point after a relaxation time from a time point when application of the program pulse is finished, the plurality of post pulses having voltage levels that increase sequentially. Programming speed and/or performance of the resistive memory device may be enhanced by accelerating resistance drift of the resistive memory cell using the plurality of post pulses having the voltage levels that increase sequentially.

Resistive memory device and programming method of the same

A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.

Non-volatile memory device including decoupling circuit

Provided is a programming method of a nonvolatile memory device, the method comprising the steps of a first programming loop including applying a first verifying voltage to word lines of a plurality of first memory cells for being programmed in a first programming state of a first target threshold voltage and detecting, from among the plurality of first memory cells, a first slow memory cell whose threshold voltage is less than the first verifying voltage, a second programming loop including applying a first program pulse to the first memory cells and applying a second program pulse to the first slow memory cell, a voltage level of the second program pulse of the second program loop being greater than a voltage level of the first program pulse of the second program loop, and a third programming loop.

Nonvolatile memory device and programming method for fast and slow cells thereof

In method of programming a nonvolatile memory device, multi-bit data are loaded into a plurality of page buffers. Multi-level cells included in a multi-level cell block are programmed to a plurality of intermediate program states including a first intermediate program state and a second intermediate program state which is higher than the first intermediate program state based on the multi-bit data. Whether the multi-level cells are programmed to the plurality of intermediate program states is verified. Cell group information for the first intermediate program state is generated by checking whether a result of the verification for the second intermediate program state satisfies a predetermined criterion. The multi-level cells are programmed to a plurality of target program states corresponding to the multi-bit data based on the cell group information.

Growing community of inventors

Hwaseong-si, South Korea

Yong-Sung Cho