Skhynix Inc.

Yong Suk Joo

Kyung Ho Chu

Soo Bin Lim

Geun Ho Choi

Soo Young Jang

Geun Il Lee

Kyu Bong Kong

A column control circuit may include a column control signal generation circuit and a column access block signal generation circuit. The column control signal generation circuit is configured to activate an input/output strobe signal when a column access block signal is deactivated. The column control signal generation circuit is configured to deactivate the input/output strobe signal when the column access block signal is activated. The column access block signal generation circuit is configured to activate the column access block signal when gap-less read commands may be inputted. The column access block signal generation circuit may deactivate the column access block signal during a period corresponding to an N-th read command among the gap-less read commands. N is an integer that is no less than 2.

Column control circuit and semiconductor device including the same

A semiconductor apparatus includes: a pad unit comprising a plurality of data input/output (I/O) pads and a plurality of error detection code pads; an error detection code (EDC) read path configured to generate a plurality of EDCs by performing an error detection operation on a plurality of data, and output the plurality of EDCs through the plurality of error detection code pads; a comparison circuit configured to generate a comparison result signal by comparing the plurality of EDCs; and a data read path configured to output the comparison result signal through any one of the plurality of data I/O pads.

Semiconductor apparatus and test system including the semiconductor apparatus

A semiconductor system may include a controller and a semiconductor device. The controller may output command/address signals. The semiconductor device may generate a plurality of control codes from the command/address signals in a test mode according to a combination of the command/address signals. The semiconductor device may output a first output datum generated by serializing the plurality of control codes, and the first output datum, through a single pad.

Test mode circuit with serialized I/O and semiconductor memory device including the same

The semiconductor device includes an input clock generator and a data input unit. The input clock generator generates an input clock signal including a first pulse and a second pulse, wherein the first pulse is generated in response to a write signal and a write latency signal and the second pulse is generated in response to an external command signal and a burst length signal. The data input unit receives data and generates first input data in response to the first pulse of the input clock signal and receives the data and generates second input data in response of the second pulse of the input clock signal.

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Yongin-si, South Korea

Yong Suk Joo