Samsung Electronics Co., Ltd.

Lg Display Co., Ltd.

Dongwoo Fine-chem Co., Ltd.

Yong-suk Choi

Seung-Beom Yoon

Yong-Tae Kim

Gee-Sung Chae

Gyoo-Chul Jo

Oh-Nam Kwon

Kyoung-Mook Lee

Yong-Sup Hwang

Seung-yong Lee

Seong-Gyun Kim

Moo-young Kim

Jae-Hwang Kim

Og-Hyun Lee

Jin-woo Choi

Seong-Su Kim

Heeseog Jeon

Jin-Woo Kim

Seung-Yong Lee

Dong-Uk Choi

Young-Chul Park

Dong-woo Lee

Jae-Yeon Lee

Joon-Woo Lee

Kyu-sang Kim

Hong-Je Cho

Young-Sam Park

Ji-won Jeong

Kwan-Tack Lim

Seong-gyun Kim

Jin-Su Kim

Seung-Hwan Chon

An image sensor includes a pixel array of pixels arranged in one or more rows and one or more columns, the pixel array configured to generate an image based on light being incident on one or more pixels of the pixel array. The image sensor includes pixel load circuitry connected to one column of pixels and including transistors serially connected to each other. The image sensor includes switches connected in parallel to separate, respective nodes between adjacent transistors. The image sensor includes image sensor processing circuitry configured to receive, from image processor circuitry, gain information indicating an intensity of light concurrently with an image being generated by the image sensor, and control at least one switch of the plurality of switches to be turned on/off to change an electrical path of a current that passes through the pixel load circuitry, based on the gain information.

Image sensors and methods of operating the same

Provided are a scan data processing method and apparatus. The method includes: performing a wireless communication connection with a predetermined user device during a scan mode; detecting user profile information corresponding to a user address of the predetermined user device; and controlling scan data based on the user profile information.

Method and apparatus for processing scan data

An etching solution for a multiple layer of copper and molybdenum includes: about 5% to about 30% by weight of a hydrogen peroxide; about 0.5% to about 5% by weight of an organic acid; about 0.2% to about 5% by weight of a phosphate; about 0.2% to about 5% by weight of a first additive having nitrogen; about 0.2% to about 5% by weight of a second additive having nitrogen; about 0.01% to about 1.0% by weight of a fluoric compound; and de-ionized water making a total amount of the etching solution 100% by weight.

Etching solution for multiple layer of copper and molybdenum and etching method using the same

A non-volatile memory device includes a control gate electrode disposed on a substrate with a first insulation layer interposed therebetween and a floating gate disposed in a hole exposing substrate through the control gate electrode and the first insulation layer. A second insulation layer is interposed between the floating gate and the substrate, and between the floating gate and the control gate.

Non-volatile memory device and methods of forming the same

A non-volatile memory device comprises an active region disposed in a predetermined region of a semiconductor substrate, a selection gate electrode crossing over the active region, and a floating gate electrode disposed on the active region parallel to the selection gate electrode and spaced apart from the selection gate electrode. The non-volatile memory device further comprises a tunnel insulating layer intervening between the active region and each of the selection gate electrode and the floating gate electrode, a separation insulating pattern intervening between the selection gate electrode and the floating gate electrode, an erasing gate electrode disposed over the floating gate electrode and crossing over the active region parallel to the selection gate electrode, and an erasing gate insulating layer intervening between the erasing gate electrode and the floating gate electrode. The selection gate electrode is formed without a photoresist pattern.

Method of forming non-volatile memory device

An etchant for removing an indium oxide layer includes sulfuric acid as a main oxidizer, an auxiliary oxidizer such as HPO, HNO, CHCOOH, HClO, HO, and a Compound A that is obtained by mixing potassium peroxymonosulfate (2KHSO), potassium bisulfate (KHSO), and potassium sulfate (KSO) together in the ratio of 5:3:2, an etching inhibitor comprising an ammonium-based material, and water. The etchant may remove desired portions of the indium oxide layer without damage to a photoresist pattern or layers underlying the indium oxide layer.

Etchant composition for indium oxide layer and etching method using the same

Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each other, the conductive spacer and the dummy spacer having round surfaces that face outward; a pair of insulating spacers formed on a sidewall of the conductive spacer and a sidewall of the dummy spacer which face each other; an ONO layer formed in a self-aligned manner between the pair of insulating spacers; a conductive layer formed on the ONO layer in a self-aligned manner between the pair of insulating spacers; and source and drain regions formed in the silicon substrate outside the conductive spacer and the dummy spacer.

Local SONOS-type nonvolatile memory device and method of manufacturing the same

A split gate type nonvolatile semiconductor memory device and a method of fabricating a split gate type nonvolatile semiconductor memory device are provided. A gate insulating layer and a floating-gate conductive layer are formed on a semiconductor substrate. A mask layer pattern is formed on the floating-gate conductive layer to define a first opening extending in a first direction. First sacrificial spacers having a predetermined width are formed on both sidewalls corresponding to the mask layer pattern. An inter-gate insulating layer is formed on the floating-gate conductive layer. The first sacrificial spacers are removed, and the floating-gate conductive layer is etched until the gate insulating layer is exposed. A tunneling insulating layer is formed on an exposed portion of the floating-gate conductive layer. A control-gate conductive layer is formed on a surface of the semiconductor substrate. Second sacrificial spacers having predetermined widths are formed on the control-gate conductive layer. A split control gate is formed in the first opening, by etching the exposed control-gate conductive layer. The remaining mask layer pattern and inter-gate insulating layer are etched until the floating-gate conductive layer is exposed. The exposed floating-gate conductive layer is etched to form a split floating gate in the first opening.

Split gate type nonvolatile semiconductor memory device, and method of fabricating the same

A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.

Flash memory device and method of manufacturing the same

A tunneling dielectric layer, a charge trapping layer, a first length defining layer, and a second length defining layer are sequentially deposited on a semiconductor substrate. These layers are sequentially patterned. Exposed both sidewalls of the first length defining layer first pattern are recessed by selective side etching. After forming a blocking layer for covering the exposed charge trapping layer and a gate layer for filling the recessed portion, the gate layer is patterned to form spacer shaped gates. Dopant regions for source and drain regions are formed on the semiconductor substrate adjacent the gates.

Method of manufacturing a semiconductor memory device

Embodiments of the invention include a gate insulating layer formed on a semiconductor substrate; a spacer-type floating gate and a spacer-type dummy pattern, which are formed on the gate insulating layer and separated apart from each other, the floating gate and the dummy pattern having round surfaces that face outward; a pair of insulating spacers, which are formed on a sidewall of the floating gate and a sidewall of the dummy pattern which face each other; a control gate formed in a self-aligned manner between the pair of insulating spacers; a tunnel insulating layer interposed between the floating gate and the control gate; and source and drain regions formed in the semiconductor substrate outside the floating gate and the dummy pattern.

Split-gate nonvolatile memory device and method of manufacturing the same

In a method of forming a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory device, a plurality of first gates may be formed on a semiconductor substrate. A plurality of charge storage spacers may be formed on the plurality of first gates so that a given charge storage spacer may be disposed on a sidewall of a given first gate. A plurality of second gates may be disposed on the plurality of first gates so that a given second gate is on a sidewall of a given first gate and covers a given charge storage spacer.

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Seoul, South Korea

Yong-suk Choi