Skhynix Inc.

Samsung Electronics Co., Ltd.

Snur & Db Foundation

Yong Soon Park

Jin Young Choi

Da Eun Kim

Seung Eun Chung

Dong Hwan Lee

Dong Woo Lee

Jin Han Kim

Won Sun Park

Seung Ki Sul

Young Jae Park

Seok-Mo Chang

Bum Jang

Sung Chan Yun

Hyeon Su Nam

Hee-Soo Jeong

Geonu Kim

A memory device in accordance with a described method of operation includes a read only memory (ROM) address controller and a suspend signal generator. The ROM address controller is configured to sequentially output a plurality of operation ROM addresses at which ROM codes to be executed in response to an operation command are stored, and to suspend output of the plurality of operation ROM addresses in response to a suspend signal. The suspend signal generator is configured to generate the suspend signal that is activated during a preset period depending on whether a suspend ROM address is identical to an operation ROM address, among the plurality of operation ROM addresses, currently being output. The suspend ROM address is an address at which a ROM code, execution of which is to be suspended, among the ROM codes, is stored.

Memory device to suspend ROM operation and a method of operating the memory device

The present technology relates to a memory device and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells, a data register connected to the memory cell array through a bit line and configured to store data sensed through the bit line, a cache register configured to cache the data stored in the data register, and a control logic configured to control a caching operation of receiving a cache read command from a memory controller and storing the data, which is stored in the data register, in the cache register, during a cache read period, in response to the cache read command, wherein the control logic controls the caching operation based on whether the cache read command is a first command received after receiving a normal read command from the memory controller.

Memory device for improving speed of cache read operation and method of operating the same

A semiconductor memory device includes a storage, a buffer, and a control logic. The storage stores a first algorithm data. The buffer stores a second algorithm data that is at least partially different from the first algorithm data. The control logic is configured to selectively receive the first algorithm data and the second algorithm data.

Semiconductor memory device and method of operating the same

A clothes dryer comprises a body, a first drying container installed in the body and configured to include a rotary drum configured to be rotatable, and a second drying container installed in the body but separated from the first drying container, and the second drying container includes an electrode plate configured to include a plurality of electrode regions, a controller configured to select an electrode region where an electric field is to be applied, among the plurality of electrode regions and an electric field is applied to the electrode region selected by the controller.

Clothes dryer

Provided are a dryer and method for controlling the same, which may appropriately and efficiently dry objects thrown into a receiving space by using high frequency electric fields and heated air. In accordance with one aspect of the present disclosure a dryer includes a main body, a drum rotationally placed inside the main body, a driver provides rotational force to the drum, an electrode part produces an electric field inside the drum, a power supplier supplies power to the electrode part, an air heater heats air, a blower supplies heated air into the drum and a controller controls the power supplier to block power supplied to the electrode part depending on a dried state of an object contained in the drum, controls the driver to rotate the drum, and controls the air heater and the blower to supply heated air into the drum.

Dryer and method for controlling the same

A memory system includes a memory device for storing data, and a controller for controlling the memory device by outputting control signals to the memory device. In the memory device, when an address of a selected operation is received in response to the control signals, the memory device simultaneously initializes a page buffer included in the memory device.

Memory system initializing page buffers and operating method thereof

A method of estimating inductance of a permanent magnet synchronous motor (PMSM) includes injecting a signal having a frequency differing from an operating frequency of the PMSM into the PMSM during sensorless operation, sensing magnitudes of current responses to the injected signal, and estimating an inductance value at which the magnitude of the sensed current response is minimal to be an actual inductance value of the PMSM, thereby estimating inductance used in the PMSM regardless of position estimation error of the PMSM and thus more accurately and reliably estimating inductance of the PMSM.

Growing community of inventors

Seoul, South Korea

Yong Soon Park