Hynix Semiconductor Inc.

Skhynix Inc.

Yong Soo Choi

Hyangkeun Yoo

Hyuk Sang Kwon

Hyung Soon Park

Sanghun Lee

Gyu Hyun Kim

Geun Min Choi

Won Mo Lee

Ho Jin Jeong

Sang Hwa Lee

Yong Wook Song

Gyu Han Yoon

A ferroelectric semiconductor device of the present disclosure includes a substrate, a ferroelectric layer disposed on the substrate, an electric field control layer that is disposed on the ferroelectric layer and has a predetermined internal electric field formed without the application of an external electric power to alter the magnitude of a coercive electric field of the ferroelectric layer, and a gate electrode layer disposed on the electric field control layer.

Ferroelectric semiconductor device

In an embodiment, a ferroelectric memory device includes a semiconductor substrate, a first ferroelectric memory cell transistor of NMOS type disposed in a first region of the semiconductor substrate, and a second ferroelectric memory cell transistor of PMOS type disposed in a second region adjacent to the first region of the semiconductor substrate. A first gate electrode layer of the first ferroelectric memory cell transistor and a second gate electrode layer of the second ferroelectric memory cell transistor are electrically connected to each other.

Ferroelectric memory device

A ferroelectric memory device is disclosed. The ferroelectric memory device includes a substrate, an indium-gallium-zinc oxide layer disposed on the substrate, a ferroelectric material layer disposed on the indium-gallium-zinc oxide layer, a gate electrode layer disposed on the ferroelectric material layer, and a source electrode layer and a drain electrode layer that are disposed the ends of the gate electrode. The indium-gallium-zinc oxide layer is recessed to form a trench at the ends of the gate electrode. The trench is filled with a conductive material to form the source electrode layer and the drain electrode layer.

Nonvolatile memory device

In a method of treating a semiconductor substrate, a plurality of active regions and a plurality of trench isolation regions are formed by selectively etching the semiconductor substrate. The semiconductor substrate is washed by providing deionized water to the semiconductor substrate. A silicon-based solution is provided to the semiconductor substrate by replacing the deionized water disposed on the semiconductor substrate with the silicon-based solution. A silicon oxide material is formed from the silicon-based solution by performing a heat treatment on the silicon-based solution and the semiconductor substrate. The silicon oxide material fills the trench isolation regions.

Method of treating semiconductor substrate

A capacitor is formed by forming a mold insulating layer with a plurality of storage node holes over a semiconductor substrate. A metal storage node is formed on the surface of each of the storage node holes in the mold insulating layer. The mold insulating layer is removed by performing the following steps: loading the semiconductor substrate with the storage node in the chamber for in-situ cleaning, rinsing, and drying processes; removing the mold insulating layer by an etchant in the chamber; then rinsing the semiconductor substrate by introducing deionized water into the chamber while discharging the etchant out of the chamber; finally rinsing the rinsed semiconductor substrate with a mixed solution of the deionized water and organic solvent; drying the finally rinsed semiconductor substrate by IPA vapor in the chamber while discharging the mixed solution of the deionized water and organic solvent out of the chamber.

Method for forming semiconductor memory capacitor without cell-to-cell bridges

A polishing pad for chemically mechanically polishing a semiconductor wafer comprises a first groove pattern circularly formed on the surface of the polishing pad, and a second groove pattern formed on the surface of the polishing pad while spirally extending from the circular center of the polishing pad to the outside so as to overlap the first groove pattern. The polishing pad further comprises a third groove pattern formed on the surface of the polishing pad while radially extending from the circular center of the polishing pad to the outside so as to overlap the first and second groove patterns. A chemical mechanical polishing apparatus comprises the polishing pad. The polishing pad of the chemical mechanical polishing apparatus has enhanced groove patterns formed on the polishing pad to provide uniform distribution of the slurry, thereby enhancing polishing speed and polishing uniformity.

Polishing pad and chemical mechanical polishing apparatus using the same

A method for reducing a thickness variation of a nitride layer in a shallow trench isolation (STI) CMP process is provided, the method including forming an active region pattern in an alignment key region of a scribe lane where a device isolation film is formed at an ISO level, and forming a dummy active region pattern substantially adjacent to a vernier key pattern in the scribe lane during formation of the vernier key pattern, wherein the dummy active region pattern is spaced apart from the vernier key pattern by a known distance. Preferably, the active region pattern and the dummy active region pattern are formed prior to the STI CMP process.

Methods for reducing a thickness variation of a nitride layer formed in a shallow trench isolation CMP process and for forming a device isolation film of a semiconductor device

Disclosed herein is a chemical mechanical polishing (CMP) method for manufacturing a semiconductor device, comprising performing partial ion implantation of dopants at different concentrations into a plurality of at least two divided regions of a wafer having a planarization-target film, and subjecting the partially ion implanted-wafer to a chemical mechanical polishing process. In accordance with the present invention, non-uniformity of the removal rate in a chemical mechanical polishing process is countervailed by dopants which are implanted at different concentrations via partial ion implantation, and thereby it is possible to polish the target film at a uniform removal rate.

Chemical mechanical polishing method for manufacturing semiconductor device

Capsulated abrasive compositions and a polishing pad using the same. More specifically, a polishing pad coated with compositions, which contain a capsulated abrasive, thereby used for planarizing interlayer insulating film formed on a semiconductor substrate by chemical mechanical polishing.

Growing community of inventors

Seongnam-si, South Korea

Yong Soo Choi