Samsung Electronics Co., Ltd.

Yong-Sik Yim

Jung-Dal Choi

Kyu-Charn Park

You-Cheol Shin

Hong-Suk Kwack

Chang-Hyun Lee

Jae-Hwang Sim

Won-Cheol Jeong

Jae-Kwan Park

Sung-Nam Chang

Hong-Soo Kim

Seong-Soon Cho

Dong-hwa Kwak

Dae-Woong Kang

Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

Semiconductor devices having a convex active region and methods of forming the same

Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby are provided. The method includes forming a pad insulation layer and an initial high voltage gate insulation layer on a first region and a second region of a semiconductor substrate respectively. The initial high voltage gate insulation layer is formed to be thicker than the pad insulation layer. A first isolation layer that penetrates the pad insulation layer and is buried in the semiconductor substrate is formed to define a first active region in the first region, and a second isolation layer that penetrates the initial high voltage gate insulation layer and is buried in the semiconductor substrate is formed to define a second active region in the second region. The pad insulation layer is then removed to expose the first active region. A low voltage gate insulation layer is formed on the exposed first active region. Accordingly, it can minimize a depth of recessed regions (dent regions) to be formed at edge regions of the first isolation layer during removal of the pad insulation layer, and it can prevent dent regions from being formed at edge regions of the second isolation layer.

Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby

A floating trap type non-volatile memory device and fabrication method thereof are provided. The floating trap type device comprises a substrate, a gate electrode formed on the substrate. A charge storage layer is interposed between the substrate and the gate electrode. A tunneling layer is interposed between the substrate and charge storage layer. The charge storage layer comprises a material having a narrower band gap than silicon nitride. The charge storage layer preferably formed of tetrahedral amorphous carbon. The potential barrier between the charge storage layer and the tunneling layer is increased by using the tetrahedral amorphous carbon as the charge storage layer. Therefore, the charge retention characteristic of the floating trap type device is improved.

Floating trap-type non-volatile memory device

A non-volatile memory device having a MONOS (Metal-oxide-nitride-oxide-semiconductor) gate structure is provided. This device includes a selection transistor and a cell transistor including a cell gate insulation layer formed in a cell array area and a low-voltage MOS transistor having a low-voltage gate insulation layer and a high-voltage MOS transistor having a high-voltage gate insulation layer formed in a peripheral circuit area. The low-voltage gate insulation layer is thinner than the high-voltage gate insulation layer. The low-voltage gate insulation layer can also be thinner than the equivalent thickness of the cell gate insulation layer.

Non-volatile memory device having a metal-oxide-nitride-oxide-semiconductor gate structure

Embodiments of the invention provide a method that includes forming a selection transistor and a cell transistor that includes a cell gate insulation layer in a cell array area. The method also includes forming a low-voltage MOS transistor having a low-voltage gate insulation layer and a high-voltage MOS transistor having a high-voltage gate insulation layer in a peripheral circuit area. The low-voltage gate insulation layer is formed thinner than the high-voltage gate insulation layer. The low voltage gate insulation layer may also be formed thinner than the equivalent thickness of the cell gate insulation layer.

Method of forming a non-volatile memory device having a metal-oxide-nitride-oxide-semiconductor gate structure

A NAND-type flash memory device for preventing punchthrough and a method for forming the same are provided. The NAND-type flash memory device includes a string selection transistor, a plurality of cell memory transistors, and a ground selection transistor being sequentially connected in series. The device further includes a bitline contact connected to a drain region of the string selection transistor, and a common source line connected to a source region of the ground selection transistor. Impurities are heavily doped to a drain-to-channel interface in the string selection transistor and a channel-to-source interface in the ground selection transistor, forming pockets for preventing punchthrough. The pockets are preferably formed using a tilted ion implantation using the vertical gate structures as masks.

Nand-type flash memory device and method of forming the same

NAND-type flash memory device and method of forming the same

A non-volatile memory device and fabrication methods thereof are provided. A first inter-gate insulating layer is formed to intervene between control gate electrodes and floating gate electrodes in a cell array area. A second inter-gate insulating layer is formed to intervene between a gate electrode and a dummy gate electrode in a peripheral circuit area. The second inter-gate insulating layer has a thickness greater than a thickness of the first inter-gate insulating layer on a top surface of the floating gate electrodes. By reducing the difference between the thickness of the first inter-gate insulating layer on sidewalls of floating gate patterns and the thickness of the second inter-gate insulating layer on a gate electrode pattern, in accordance with the invention, any etching damage to the substrate in the peripheral circuit area can be considerably reduced or prevented during the fabrication process.

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Kyunggi-do, South Korea

Yong-Sik Yim