Samsung Electronics Co., Ltd.

Yong-Sik Seok

Dong-soo Jun

Jae-Gu Roh

Dong-jae Lee

Do-Chan Choi

Dong-Sun Min

Seung-Cheol Oh

Kyung-Youl Min

Young-Gwon Choi

Chan-Sok Park

A semiconductor memory device using a low level supply voltage has separation gates for isolating adjacent bit lines. The device may be constructed with a circuit for receiving a high voltage supplied by a high voltage generator resident upon the chip so as to provide the separation gates with a voltage increased at least by the amount of the threshold voltage of the separation gates over the supply voltage.

Circuit for generating a clock signal to separate bit lines in a

A semiconductor memory device has adjacent memory arrays and isolation transistors disposed between a common bit sense amplifier and the memory arrays. An isolation control circuit according the present invention generates the power supply voltage Vcc (not the boost voltage Vpp) during the burn-in mode of operation, so that the gate oxide layer of the isolation transistors is prevented from being destroyed or deteriorated.

Circuit for controlling isolation transistors in a semiconductor memory

A high density semiconductor device is provided with an improved voltage pumping (bootstrapping) circuit. The voltage pumping circuit generates at an initial power-up state a first output voltage which is substantially identical to the memory device source supply voltage. The pumping circuit then pumps the first output voltage up to a second output voltage which is higher than the first output voltage. The pumping operation is achieved prior to or upon the semiconductor memory device being enabled in response to a series of pulses output from an oscillator.

Voltage pumping circuit for semiconductor memory devices

A semiconductor memory device divided into a number of main blocks each main block having a number of subblocks selects a single main block and enables the subblocks of the selected main block, so as to reduce the power consumptions. The semiconductor memory device includes a block selector for selecting one of the main blocks in response to row address signals, a number of first boost circuits for selecting the subblocks of the selected main block in response to the row address signals, and a number of second boost circuits adapted to be disabled in response to the row address signals.

Semiconductor memory device having a block selection function with low

A column redundancy circuit for a semiconductor memory device, e.g., a DRAM, which includes a normal memory array comprised of a plurality of memory blocks each comprised of a matrix of rows and columns of memory cells, with at least two of the memory blocks sharing common columns, and with at least one of the columns being defective, in the sense of being connected to at least one memory cell which has been determined to be defective. The column redundancy circuit includes a plurality of redundant columns, block selection control circuit which is programmed to generate a first output signal in response to receipt of a memory block address signal corresponding to one or more of the memory blocks which contain the defective column, a column address decoder which is programmed to generate a second output signal in response to receipt of both the first output signal and a column address signal corresponding to the defective column, and, a redundant column driver circuit which is responsive to the second output signal for activating a predetermined one of the redundant columns, to thereby repair the defective column. In a preferred embodiment, the block selection control circuit and the column address decoder each include a plurality of fuses and are each programmed by means of a selected one or more of their fuses being blown, e.g., by use of a laser.

Growing community of inventors

Daegu, South Korea

Yong-Sik Seok