Infineon Technologies North America Corp.

International Business Machines Corporation

Samsung Electronics Co., Ltd.

Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Yong Siang Tan

Richard O Henry

Judson Robert Holt

Henry K Utomo

Jin-Ping Han

Chung Woh Lai

Eric C Harley

O Sung Kwon

Richard J Murphy

Sang Jine Park

Zainab Ismail

Yin-Min Felicia Goh

Oh Jung Kwon

Ling Zhi Tan

Sin Ping Chiew

An integrated circuit system includes providing an integrated circuit wafer; applying a first cleaning solution over the integrated circuit wafer; and applying a second cleaning solution over the integrated circuit wafer to prevent or remove a defect resulting from the first cleaning process.

Integrated circuit system with clean surfaces

A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25&#xb0; C. to about 65&#xb0; C.

Semiconductor fabrication process including an SiGe rework method

Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, sacrificial nitride spacers on opposing sidewalls of the gate electrode and source/drain regions, which are self-aligned to the sacrificial nitride spacers, on a semiconductor substrate. The sacrificial nitride spacers are selectively removed using a diluted hydrofluoric acid solution having a nitride-to-oxide etching selectivity in excess of one. In order to increase charge carrier mobility within a channel of the field effect transistor, a stress-inducing electrically insulating layer is formed on opposing sidewalls of the gate electrode. This insulating layer is configured to induce a net tensile stress (NMOS) or compressive stress (PMOS) in the channel.

Method of forming field effect transistors using diluted hydrofluoric acid to remove sacrificial nitride spacers

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Yong Siang Tan