Samsung Electronics Co., Ltd.

Korea Advanced Institute of Science and Technology

Il-yang Pharm. Co., Ltd

University of California

Park Systems Corporation

Research & Industrial Cooperation Group

Yong-Seok Kim

Soon-Young Yoon

June Moon

Jung-Hwan Kim

Tae-Hyun Kim

Hun-Hyeoung Leam

Seok-Woo Nam

Tea-Kwang Yu

Hyun Namkoong

Jae-Hee Cho

Kohji Kanamori

Kwan-Hee Roh

Jun-Hee Lim

Ki-Young Han

Keun-Chul Hwang

Kyung-Hwan Lee

Ji-Ho Cho

Won-Bo Shim

Byoung-taek Kim

Sun-gyung Hwang

Tae-young Kim

In-Seok Hwang

Chang-seok Kang

Sung-Soo Hwang

Young-Hoon Kwon

Sung-Il Chang

Su-Jin Ahn

Chung-Ryul Chang

Jae-Sung Sim

Si-Hyun Park

Jae-Woo So

Ji-Yeong Hwang

Yeong-taek Lee

Ki-Nam Kim

Ki-Tae Park

Sang-Wook Kwon

Joo-Hyun Lee

Joon-Hee Lee

Dong-Ho Cho

Jae-Hoon Jang

Kyung-Joo Suh

Tae-hun Kim

Kwang-soo Kim

Dong-Yeon Kim

Jong-Ho Park

Jong-Won Kim

Sin-Ae Kim

Chi-Sung Bae

Yeonkyu Jeong

Hakbong Lee

Bosang Kim

Woo Jin Na

Min-kyung Bae

Byoung-Cheol Han

Oh-Hyun Jo

Sun-Ahe Lee

Kyung Shik Roh

Hyun-Kyu Yu

Chi-Woo Lim

Shin Hyoung Kim

Jae-Weon Cho

Beom-Sik Bae

Ji-Yun Seol

Ki-Hyun Hwang

Sung-woo Park

Hyun-Cheol Park

Sung-Ho Lee

Jae-Won Kim

Won-Il Roh

Ji-Hyun Park

Hyun-jung Kim

Sung-Hoi Hur

Sang Sik Yoon

Hyun Soo Jung

Seok-Ki Ahn

Jong-In Kim

Hyun-Suk Kim

Byoung-Ha Yi

Hyon-Goo Kang

Sang-Hoon Sung

Sang-il Park

Hong-suk Kim

Jae-Hyok Lee

In-Soo Kim

Yeon Kyu Jeong

Soong-Yoon Choi

Hun-hyeong Lim

Ju-Seung Lee

Jong-won Kim

Won-Jin Kim

Jin-hyun Shin

Young-Han Kim

Kyong Su Kim

Soo-Yong Jeon

Byoung-Gi Jang

Hak Bong Lee

Kwang-Taik Kim

Sang Han Chung

Eun-Sun Choi

Hyoun-Kuk Kim

A program method of a nonvolatile memory device that performs a plurality of program loops is provided. At least one of the plurality of program loops includes dividing a channel of a selected cell string into a first side channel and a second side channel during a first interval and a second interval, turning off a string selection transistor of the selected cell string by applying a string select line voltage of a first level during the first interval, and boosting a first voltage of the first side channel and a second voltage of the second side channel, and turning on the string selection transistor by applying the string select line voltage of a second level different from the first level during the second interval, and performing a hot carrier injection (HCI) program operation on a selected memory cell corresponding to the first side channel or the second side channel.

Nonvolatile memory device and program method of the same

Provided is a cleaning system including: a robot cleaner including a dust collecting device having a dirt outlet and an outlet door configured to open and close the dirt outlet; and a station including a collecting device configured to generate a suction force to suction dirt of the duct collecting device and a lever device provided with a lever configured to be fixable to the outlet door as the outlet door is being opened to allow the collecting device and the dust collecting device to communicate with each other, and a lever driving source configured to generate power for driving the lever.

Robot cleaner, station, and cleaning system

In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

Vertical semiconductor devices and methods of manufacturing the same

A vertical memory device includes gate electrodes on a substrate and a first structure. The gate electrodes may be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate. The first structure extends through the gate electrodes in the first direction, and includes a channel and a variable resistance structure sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. The variable resistance structure may include quantum dots (QDs) therein.

Vertical memory devices

In a method of writing data in a nonvolatile memory device including a plurality of cell strings, each of the plurality of cell strings includes a plurality of memory cells disposed in a vertical direction. A program target page is divided into a plurality of subpages. The program target page is connected to one of a plurality of wordlines. Each of the plurality of subpages includes memory cells that are physically spaced apart from one another. A program operation is sequentially performed on the plurality of subpages. A program verification operation is performed on the program target page including the plurality of subpages at a time.

Method of writing data in nonvolatile memory device, with divided subpages or subblocks, and method of erasing data in nonvolatile memory device with divided subpages or subblocks

A vertical semiconductor device includes conductive pattern structures extending in a first direction, a trench between two adjacent conductive pattern structures in a second direction crossing the first direction, a memory layer disposed on sidewalls of the trench, first insulation layers disposed in the trench and spaced apart from each other in the first direction, channel patterns disposed on the memory layer and in the trench and spaced apart from each other in the first direction, and etch stop layer patterns disposed in the trench. Each conductive pattern structure includes conductive patterns and insulation layers alternately stacked on an upper surface of the substrate. Each etch stop layer pattern is disposed between a corresponding first insulation layer and the blocking dielectric layer. Etch stop layer patterns are spaced apart from each other in the first direction.

Vertical semiconductor devices

A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, a common source extension structure including a first semiconductor layer having an n-type conductivity and a gate insulating layer between the substrate and the channel structures, a plurality of gate electrodes on the common source extension structure and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension structure and including a second semiconductor layer having an n-type conductivity. An upper portion of the common source extension structure has a first width, and a lower portion of the common source extension structure has a second width smaller than the first width.

Semiconductor device including vertical channel layer

A vertical semiconductor device includes a conductive pattern structure in which insulation patterns and conductive patterns alternately and repeatedly stacked on the substrate. The conductive pattern structure includes an edge portion having a stair-stepped shape. Each of the conductive patterns includes a pad region corresponding to an upper surface of a stair in the edge portion. A pad conductive pattern is disposed to contact a portion of an upper surface of the pad region. A mask pattern is disposed on an upper surface of the pad conductive pattern. A contact plug penetrates the mask pattern to contact the pad conductive pattern.

Vertical semiconductor devices and method of manufacturing the same

The present invention relates to a 5-generation (5G) or pre-5G communication system to be provided to support a higher data transmission rate beyond a 4-generation (4G) communication system such as long term evolution (LTE). The present invention relates to a method for performing a random access process by a base station in a communication system supporting a beamforming scheme, the method comprising the steps of: transmitting information on a reception beam corresponding to each unit time interval; performing, in each unit time interval, a reception beam sweeping process on the basis of the reception beam corresponding to each unit time interval; stopping the reception beam sweeping process when, in the process of performing the reception beam sweeping process, it is detected that a random access process should be performed with a UE in a specific unit time interval; and performing the random access process with the UE.

Apparatus and method for performing random access process in communication system supporting beamforming scheme

A vertical semiconductor device includes a conductive pattern structure, a memory layer, a pillar structure, and second and third insulation patterns. The conductive pattern structure includes conductive patterns and insulation layers, and may include a first portion extending in a first direction and a second portion protruding from a sidewall of the first portion. The conductive pattern structures are arranged in a second direction perpendicular to the first direction to form a trench therebetween. The memory layer is formed on sidewalls of the conductive pattern structures. The pillar structures in the trench, each including a channel pattern and a first insulation pattern formed on the memory layer, are spaced apart from each other in the first direction. The second insulation pattern is formed between the pillar structures. The third insulation pattern is formed between some pillar structures, and has a shape different from a shape of the second insulation pattern.

Growing community of inventors

Suwon-si, South Korea

Yong-Seok Kim