Skhynix Inc.

Hynix Semiconductor Inc.

Yong Seok Eun

Kyong Bong Rouh

Eun Shil Park

Tae Kyun Kim

Min Yong Lee

Su Ho Kim

An Bae Lee

Young Bog Kim

Hye Jin Seo

Jun Soo Chang

Jun Ki Kim

Baek Mann Kim

Su Jin Chae

Min-Yong Lee

Hai Won Kim

Hyung Kyun Kim

Young Jin Son

Keum-Bum Lee

Sung Hoon Jung

Heon-Yong Chang

A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern.

Semiconductor devices having polysilicon gate patterns and methods of fabricating the same

A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.

Method for forming impurity region of vertical transistor and method for fabricating vertical transistor using the same

A buried junction is formed in a vertical transistor of a semiconductor device. Wall bodies are formed from a semiconductor substrate, the wall bodies protruding while having a first side surface and a second side surface in the opposite side of the first side surface; forming a one side contact mask having an opening which selectively opens a portion of the first side surface of the wall body; and forming a first impurity layer and a second impurity layer surrounding the first impurity layer by diffusing impurities having different diffusivities into the portion of the first side surface exposed to the opening.

Method for manufacturing vertical transistor having buried junction

A method for opening a one-side contact region of a vertical transistor is provided. The one-side contact region of the vertical transistor is opened using a polysilicon layer, a certain portion of which can be selectively removed by a selective ion implantation process. In order to selectively remove the polysilicon layer formed on one of both sides of an active region, at which the one-side contact is to be formed, impurity ion implantation is performed in a direction vertical to the polysilicon layer by a plasma doping process, and a tilt ion implantation using an existing ion implantation process is performed. In this manner, the polysilicon layer is selectively doped, and the undoped portion of the polysilicon layer is selectively removed.

Method for opening one-side contact region of vertical transistor and method for fabricating one-side junction region using the same

A dual polysilicon gate is fabricated by, inter alia, forming a polysilicon layer doped with impurities of a first conductivity type on a substrate having a first region and a second region, forming a mask pattern that covers the polysilicon layer in the first region and leaves the polysilicon layer in the second region, injecting impurities of a second conductivity type into the polysilicon layer in the second region left exposed by the mask pattern. Removing the mask pattern, and patterning the polysilicon layer to form a first polysilicon pattern in the first region and a second polysilicon pattern in the second region. The second polysilicon pattern is formed to have protrusions that laterally protrude from sidewalls thereof. Subsequently, impurities of the second conductivity type are injected into the substrate in the second region and into the protrusions of the second polysilicon pattern.

Methods of fabricating a dual polysilicon gate and methods of fabricating a semiconductor device using the same

A semiconductor memory device includes an active region protruding upward from a substrate, wherein the active region is arranged next to a trench on the substrate, a first impurity region formed at an upper portion of the active region, a second impurity region formed at a lower portion of the active region, a gate dielectric layer formed along a side of the active region between the first impurity region and the second impurity region, a gate electrode layer formed on the gate dielectric layer, a buried bit line formed at a lower portion of the trench, and a polysilicon layer formed over the buried bit line, wherein the polysilicon layer electrically connects the buried bit line with the second impurity region.

Semiconductor memory device having vertical transistor and buried bit line and method for fabricating the same

A phase change memory device and a method for manufacturing the same. The method includes the steps of defining bottom electrode contact holes by removing portions of an insulation layer, to expose bottom electrodes, on a semiconductor substrate on which the bottom electrodes and the insulation layer are sequentially formed; forming amorphous silicon spacers on inner sidewalls of the bottom electrode contact holes; and forming bottom electrode contacts in the bottom electrode contact holes.

Phase change memory device and method for manufacturing the same

A gate structure of a semiconductor device comprising a silicon substrate having a field oxide film, a plurality of gates formed by sequentially stacking a first gate dielectric film, a first gate conductive film, and a gate silicide film on the silicon substrate. a thermal oxide film formed on a side of the first gate conductive film, a plurality of trenches formed between the gates, a second gate oxide film formed on an interior wall of each trench; and a second conductive film formed in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film and the thermal oxide film.

Gate structure of semiconductor device

Provided is a method for fabricating a transistor in a semiconductor device. The method includes forming an etch stop layer pattern over a semiconductor substrate; forming a semiconductor layer for covering the etch stop layer pattern; forming a recess trench that exposes an upper surface of the etch stop layer pattern by etching the semiconductor layer pattern; removing the etch stop layer pattern exposed in the recess trench; and forming a gate that fills the recess trench.

Method for fabricating transistor in a semiconductor device utilizing an etch stop layer pattern as a dummy pattern for the gate electrode formation

A method for manufacturing a semiconductor device having recess gates includes forming an etch stop film on a semiconductor substrate; forming an etch stop film pattern selectively exposing the semiconductor substrate by patterning the etch stop film; forming a semiconductor layer on the semiconductor substrate; forming a hard mask film pattern exposing regions, for forming trenches for recess gates, on the semiconductor substrate; removing the semiconductor layer using the hard mask film pattern as a mask until the etch stop film pattern is exposed; forming the trenches for recess gates by removing the etch stop film pattern from the semiconductor substrate; and forming gate stacks, each of which is formed in the corresponding one of the trenches for recess gates.

Method for manufacturing semiconductor device having recess gate

Disclosed herein is a method for fabricating a semiconductor memory device that can prevent oxidation of bit lines when forming an interlayer dielectric for isolating the bit lines. The bit line is formed on a semiconductor substrate where an underlying structure is formed. A silicon on dielectric (SOD) layer is formed on the resulting structure where the bit line is formed. A heat treatment can be performed on the SOD layer with a partial pressure ratio of water vapor (HO) to hydrogen (H) in a range of about 1&#xd7;10to about 1.55 at a temperature in a range of about 600&#xb0; C. to about 1,100&#xb0; C.

Method for fabricating semiconductor memory device

Disclosed herein is a method for forming a gate structure of a semiconductor device. The method comprises forming a plurality of gates including a first gate dielectric film, a first gate conductive film, and a gate silicide film sequentially stacked on a silicon substrate having a field oxide film, forming a thermal oxide film on a side of the first gate conductive film, etching the silicon substrate exposed between the plurality of gates to a predetermined depth to form a plurality of trenches, forming a second gate oxide film on the interior wall of the trenches, and forming a second gate conductive film in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film, and the thermal oxide film.

Method of forming gate structure of semiconductor device

Disclosed is a method of manufacturing semiconductor devices, which can improve electrical characteristics of semiconductor devices. The method of manufacturing comprises the following steps of: forming a plurality of gates on a semiconductor substrate; forming an insulation layer on an entire surface of the semiconductor substrate to coat the plurality of gates; selectively removing the insulation layer by using a first mask pattern to form a contact hole, which exposes a source/drain junction and a conductive layer in a portion of the gates in the semiconductor substrate; removing the first mask pattern and forming a second mask pattern on the selectively removed insulation layer, the second mask pattern exposing the p+ source/drain junction in the semiconductor substrate; implanting ion into the p+ source/drain junction in the semiconductor substrate by using the second mask pattern as a mask; removing the second mask pattern and rapid thermal annealing the entire substrate in a activation temperature range of dopant which is implanted in the ion implantation step; and burying the contact hole with conductive material to form a bit line contact plug. The invention can effectively reduce bit line contact resistance but raise resistance uniformity without variation in related techniques such as etching and contact material for forming contacts.

Growing community of inventors

Seongnam-si, South Korea

Yong Seok Eun