Samsung Electronics Co., Ltd.

Yong-Seok Chung

Gwan-Hyeob Koh

Gwanhyeob Koh

Yongkyu Lee

Yoonjong Song

Kil-Ho Lee

Ki-seok Suh

Yoon-Jong Song

Jae-Chul Shim

Jae-Hyun Park

Jeong-Uk Han

Sang-hoon Park

Yong-kyu Lee

Bo-young Seo

Jae-Min Yu

Kwan-Jong Roh

Young-cheon Jeong

Byeong-Cheol Lim

A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.

Magnetoresistive random access memory device and method of manufacturing the same

The inventive concepts provide a method for forming a hard mask pattern. The method includes forming a hard mask layer on an etch target layer disposed on a substrate, forming a photoresist pattern having an opening exposing one region of the hard mask layer, performing an oxygen ion implantation process on the one region using the photoresist pattern as a mask to form an oxidized portion in the one region, and patterning the hard mask layer using the oxidized portion as an etch mask.

Method for forming a hard mask pattern and method for manufacturing a semiconductor device using the same

A resistive memory apparatus includes a memory cell array having a plurality of memory cells and a first ground switch. The plurality of memory cells are arranged in a plurality of rows and a plurality of columns, and each memory cell in a first column of the plurality of memory cells is connected between a first bitline and a first source line. The first ground switch is connected in parallel with the first source line, and the first ground switch is configured to selectively provide a first current path from the first bitline to ground through a selected memory cell in the first column of the plurality of memory cells and the first source line, the current path traversing only a portion of the first source line.

Memory apparatuses having ground switches

In a method of manufacturing a semiconductor device, a tunnel insulation layer is formed on a substrate. A charge trapping layer is formed on the tunnel insulation layer. A protection layer pattern or a mold is formed on the charge trapping layer. Charge trapping layer patterns are formed on the tunnel insulation layer by etching the charge trapping layer using the protection layer pattern or the mold. The charge trapping layer patterns may be spaced apart from each other. Blocking layers are formed on the charge trapping layer patterns, respectively. A gate electrode is formed on the blocking layers and the tunnel insulation layer using the protection layer pattern or the mold.

Method of manufacturing a semiconductor device

A method for controlling a data read/write operation of a disk drive recording device provided with re-allocated reserve sectors as a substitute for defective sectors, includes the steps of: reading data written on the reserve sectors when turning the power on and further storing the data, and disposing the data stored after being retrieved from the re-allocated reserve sectors as a substitute for defective sectors to the rear of data retrieved from a sector preceding the defective sector when accessing a random data section containing the defective sector, and further transferring the resulting data.

Method for controlling data reading/writing on random data section

Growing community of inventors

Seoul, South Korea

Yong-Seok Chung