Texas Instruments Corporation

Yong Seok Choi

James Walter Blatchford

Thomas J Aton

Ping Jiang

William Wesley Dostalik

Jeannette Michelle Jacques

A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin for the gate level interconnects of a width near the critical dimension. Off-axis illumination, as used in the photolithography of deep sub-micron critical dimension, is facilitated by the patterned features having a preferred orientation in a common direction, with a pitch constrained to within a relatively narrow range. Interconnects in that same gate level, for example 'field poly' interconnects, that run parallel to an array of gate elements are placed within a specified distance range from the ends of the gate elements, or at a distance sufficient to allow sub-resolution assist features.

Control of local environment for polysilicon conductors in integrated circuits

A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width Wover an active area and a neighboring dummy feature having a line width 0.8 Wto 1.3 W. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is &#x2267;2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.

Gate CD control using local design on both sides of neighboring dummy gate level features

A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width Wover an active area and a neighboring dummy feature having a line width 0.8Wto 1.3W. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is &#x2267;2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.

A method of forming a dual damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using a tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

Poison-free and low ULK damage integration scheme for damascene interconnects

A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using the tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

The present application is directed to apparatus and methods for determining a magnitude of defocus and a direction of defocus for a photolithography process. A sub-resolution feature on a reticle which is not printed on a wafer at the best focus offset, but is formed on a wafer at some defocus during the photolithography process is analyzed to determine the magnitude and direction of defocus. The magnitude and direction of defocus are used to adjust the photolithography process to an optimal focus based on the determined magnitude of defocus and the determined direction of defocus.

Defocus determination method using sub-resolution feature (SRF) printing

The present disclosure is directed to a method for monitoring focus of a photolithography system. The method comprises providing a substrate and depositing a photoresist layer on the substrate. At least one photomask is provided comprising one or more forbidden pitch photomask patterns formed thereon. The forbidden pitch patterns are imaged in the photoresist layer by exposing the photoresist layer to radiation through the at least one photomask. The imaged forbidden pitch patterns are developed in the photoresist. Focus error information regarding the imaging process can be determined using the developed forbidden pitch patterns.

Method of monitoring focus in lithographic processes

Exemplary embodiments provide a tri-layer resist (TLR) stack used in a photolithographic process, and methods for resist reworking by a single plasma etch process. The single plasma etch process can be used to remove one or more portions/layers of the TLR stack that needs to be reworked in a single process. The removed portions/layers can then be re-formed and resulting in a reworked TLR stack for subsequent photo-resist (PR) processing. The disclosed plasma-etch resist rework method can be a fast, simple, and cost effective process used in either single or dual damascene tri-layer patterning processes for the fabrication of, for example, sub 45-nm node semiconductor structures.

Tri-layer plasma etch resist rework

A system and method of preventing pattern lifting during a trench etch/clean process is disclosed. A first layer comprising a first dip is formed over a first via pattern. A trench resist layer is formed. The trench resist layer is patterned with a trench reticle to produce a second via pattern in the trench resist layer over the first via pattern. A photo resist over the first via pattern is opened during a trench processing. Thus, an additional pattern added on a trench pattern reticle is used to open, i.e., remove resist over, a huge via feature area causing under layer dip.

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McKinney, TX, United States of America

Yong Seok Choi