Korea Telecommunication Authority

Skhynix Inc.

Samsung Electro-mechanics Co., Ltd.

University of Seoul Industry Cooperation Foundation

Yong S Moon

Soon Hwa Jang

Yong Ju Kim

Jong Ho Jung

Jong Su Yi

Si Jin Kim

Hark Lim Choi

Dong Ha Kim

Jong Myung Park

Kwang Joe Jeon

Jong Gon Jung

A latency control circuit includes a clock delay configured to output a plurality of serial delay signals obtained by serially delaying an input clock signal with the same intervals, a deviation information generating unit configured to generate a deviation information on the basis of a delay value, which the clock signal undergoes in a chip, and latency information, a clock selector configured to output a plurality of clock selection signals based on the plurality of serial delay signals and the deviation information, a command signal processing unit configured to generate a read signal based on an input command signal, and output a variable delay duplication signal by variably delaying the read signal, and a latency shifter configured to output a latency signal by combining the plurality of clock selection signals with the variable delay duplication signal.

Latency control circuit and semiconductor device including the circuit

Disclosed is an apparatus for projection display using reflection type LCDs. The apparatus for projection display using reflection type LCDs according to the invention comprises an illuminating device including a lamp and a polarizing element for illuminating S wave or P wave, a color splitter/synthesizer, including the reflection type LCDs for providing an image corresponding to an inputted image and converting a polarizing state of incident light when reflecting the light, a retarder stack for differentiating the polarized state of a predetermined color from the incident light, and polarizing beam splitters composed of a material having a photoelastic constant less than 0.03&times;10 mm /N at a wavelength of 589.3 nm and a minimum transmittance higher than 90% in transmitting the thickness of 25 mm at a wavelength ranged 0.42 &mgr;m-0.70 &mgr;m for performing color split, color synthesis and analysis, and a projector for projecting the image passed through the color splitter/synthesizer onto a screen.

Apparatus for projection display using reflection type LCD

A scanning format conversion circuit for performing the mutual conversion between a progressive scanning format and a zig-zag scanning format to read or write N.times.N discrete cosine transform coefficients from or into a memory in a coding process or a decoding process of a video system. The scanning format conversion circuit comprises a pure logic circuit including an up/down counting circuit, a down counting circuit, first to third selection circuits, a comparison circuit, a phase change circuit, and an accumulation circuit. With this construction, the mutual conversion between the progressive scanning format and the zig-zag scanning format is performed on the basis of the rule between the input orders and the actual positions of the discrete cosine transform coefficients. Therefore, the scanning format conversion circuit is capable of simplifying the implementation of ASIC and performing the scanning format conversion operation regardless of a block size.

Conversion circuit for mutually converting between progressive scan and

An improved motion vector extractor comprising a first pixel delay element for delaying pixel data of the previous frame by a one pixel interval, a second pixel delay element for delaying the pixel data of the previous frame by a horizontal line interval of a seek block, a third pixel delay element for delaying the pixel data of the previous frame by a seek block horizontal line and one pixel interval, an interpolation circuit for combining the pixel data of the previous frame and the delayed pixel data of the previous frame from the first to third pixel delay elements to produce at least one interpolation pixel data positioned between adjacent ones thereof, a fourth pixel delay element for delaying pixel data of the present frame to produce rectangularly arranged pixel data of the present frame, a plurality of MAD detectors, each of the plurality of MAD detectors subtracting a corresponding one of the interpolation pixel data from the interpolation circuit from a corresponding one of the rectangularly arranged pixel data of the present frame from the fourth pixel delay element to produce an MAD with respect to the corresponding pixel data of the present frame, and a comparator for comparing the MADs from the plurality of MAD detectors with one another and extracting a motion vector in accordance with the compared result.

Motion vector estimator

Growing community of inventors

Seoul, South Korea

Yong S Moon