Raydium Semiconductor Corporation

Sunplus Technology Co., Ltd.

Parade Technologies, Ltd.

Yong-Nien Rao

Shih-Tzung Chou

Yu Kuang

Ko-Yang Tso

Chin-Chieh Chao

Hui-Wen Miao

Chih-Yu Lee

Chun-Lin Hou

Yu-Lung Lo

You-Ben Yin

Hua Qin

Zong-Lin Wu

Chia-Hsien Lin

A display panel subsystem adaptively employs one of three types of input offset voltage cancellation modes based on an analysis of gray level values of sub-pixels for each row un a frame of image data. The system selects a candidate row within a selected group of rows and applies a first chopper mode to each sub-pixel in the candidate row. Under a row-based mode, the system applies a second chopper mode to each sub-pixel included in a row having gray level values matching the candidate row. Under a per-column row-based mode, the system applies the row-based mode on a per-column basis. Under a sub-pixel-wise mode, for each column, the system changes a chopper mode applied to a sub-pixel in a subsequent row relative to the last state of the chopper mode in a row having the same gray level value as a corresponding sub-pixel in the subsequent row.

Adaptive spatial offset cancellation of source driver

A capacitance measurement circuit includes an operation amplifier; a reference capacitor having a first terminal coupled to a first input terminal of the operation amplifier and a second terminal selectively coupled to a first or second reference voltage; a sensor capacitor having a first terminal coupled to a second input terminal of the operation amplifier and a second terminal selectively coupled to the first or second reference voltage; an approximation unit having an output terminal and an input terminal coupled to an output terminal of the operation amplifier; a conversion unit having an output terminal and an input terminal coupled to the output terminal of the approximation unit; and a coupling capacitor having a first terminal coupled to the first or second input terminal of the operation amplifier and a second terminal coupled to the output terminal of the conversion unit.

Capacitance measurement circuit and method therefor

A method for generating chopper-stabilized signals includes the following steps. First, a voltage polarity control signal is received. Next, the voltage polarity control signal is sampled to obtain a sampling signal, and a voltage transformation manner of the voltage polarity inversion of the voltage polarity control signal is judged according to the sampling signal. Then, a frame transformation signal template is obtained according to the voltage transformation manner of the voltage polarity inversion of the voltage polarity control signal and the sampling signal. Next, the frame transformation signal template is compared with the sampling signal and a frame transformation signal is generated. Then, a first chopper-stabilized signal is outputted according to the frame transformation signal and the voltage polarity control signal.

Apparatus and method for generating chopper-stabilized signals

The invention discloses a touch input device and a touch sensor circuit. The touch input device includes a touch panel, a selection module and a differential detection module. The touch panel includes a plurality of capacitive nodes thereon. The selection module is electrically connected with the capacitive nodes of the touch panel. The selection module selects a first capacitive node and a second capacitive node from the capacitive nodes. The second capacitive node is close to the first capacitive node. The differential detection module, electrically connected to the selection module, is used for detecting a capacitance difference between the first capacitive node and the second capacitive node. According to the capacitance difference, the differential detection module generates a touch detection signal.

Touch input device and touch sensor circuit

The invention discloses a driving apparatus for driving an LCD. The driving apparatus comprises a voltage control unit, an operating unit, a resistance unit, and a voltage selection unit. The operating unit comprises two sets of buffers formed by a plurality of operational amplifiers in negative feedback circuit. The two sets of buffers selectively receive positive polarity voltages and negative polarity voltages respectively. The voltage selection unit is provided with the positive polarity voltages and negative polarity voltages through the operating unit and the resistance unit. The voltage selection unit selectively provides the pixels of the LCD with the positive polarity voltage and the negative polarity voltage. Accordingly, each of the pixels is provided either with the positive polarity voltages or the negative polarity voltages by one of the two sets of buffers.

LCD driving apparatus and method

A power-on screen pattern correcting apparatus is for correcting start output data of output terminals of a source driver such that a power-on screen pattern of a display is substantially uniform. The correcting apparatus comprises a flip-flop, a first logic unit and a second logic unit. The flip-flop controls a level of an inner signal to be substantially equal to a low signal level in response to a low level of a power start signal. The first logic unit enables a first signal in response to the low level of the inner signal or a low level of a high-impedance control signal. The second logic unit enables a second signal such that the output terminals are coupled to a charge sharing line and the power-on screen pattern is uniform in response to the low level of the inner signal or a low level of a charge-sharing control signal.

Power-on screen pattern correcting apparatus and source driver using the same

A power management circuit includes a regulator circuit, a first frequency compensation circuit, a first switch circuit and a detection circuit. The regulator circuit includes a signal output end. The first switch circuit is turned on in response to an enabled first control signal such that the first frequency compensation circuit is coupled to the regulator circuit. The detection circuit determines whether an output capacitor is coupled to the signal output end, and generates the enabled first control signal to turn on the first switch circuit and connect the first frequency compensation circuit to the regulator circuit when the output capacitor is not coupled to the signal output end. Therefore, the regulator circuit is frequency compensated by the first frequency compensation circuit.

Power management circuit and method of frequency compensation thereof

A TFT-LCD capable of repairing discontinuous lines includes a repairing circuit, which includes a plurality of repairing OP amplifiers and a high-impedance detecting unit. The high-impedance detecting unit detects states of input terminals of the OP amplifiers. The high-impedance detecting unit enables a control signal to enable the OP amplifier when the input terminal is not at floating state. The high-impedance detecting unit disables the control signal to disable the OP amplifier when the input terminal is at floating state, so that no output competition between the OP amplifiers is generated.

TFT-LCD capable of repairing discontinuous lines

A receiving circuit is provided for receiving a data signal and a clock signal, which are RSDS signals, and outputting an output data signal to a data driver. The receiving circuit includes a data comparator, a data intermediate circuit, a clock comparator, a clock intermediate, and a flip-flop. The data comparator, driven with a data bias current, receives the data signal, and outputs a compared data signal. The clock comparator, driven with a clock bias current, receives the clock signal, and outputs a compared clock signal. The flip-flop receives the compared data signal via the data intermediate circuit and the compared clock signal via the clock intermediate circuit. The phase difference between the compared data signal and the compared clock signal is improved by adjusting the data and the clock bias currents.

Receiving circuit and method thereof

Disclosed is a timing generator of panel display and polarity arrangement control signal generation method therefor. The timing generator comprises a storage unit for storing a plurality of sets of polarity data and corresponding PAC signals, an operation unit for receiving display data, the sets of polarity data, and a corresponding PAC signal so that the operation unit can perform an inner product operation with respect to the polarity data and the display data for obtaining a sum of coupling voltages, and a comparison unit for comparing the sum of coupling voltages with a predetermined value, and outputting the PAC signal corresponding to the polarity data to a data driver if the sum of coupling voltages is smaller than the predetermined value.

Growing community of inventors

Hsinchu, Taiwan

Yong-Nien Rao