Skhynix Inc.

Yong Mi Kim

Jae In Lee

Chang Hyun Kim

Jaeil Kim

Jae Woong Yun

Jeong Hun Lee

Sun Ho Kim

Jae Il Kim

Jeong Tae Hwang

Young Ook Song

Sang Uhn Cha

Kihun Kwon

Jae Hun Lee

A memory may include a memory core; a first ECC engine configured to correct an error having a first pattern, the error occurring in read data read from the memory core; and a second ECC engine configured to correct an error having a second pattern, the error occurring in the read data read from the memory core. One of the first ECC engine and the second ECC engine may be selectively activated based on an address used to access the memory core.

Memory including ECC engine

A semiconductor device includes an error correction circuit and a write operation control circuit. The error correction circuit generates corrected data and an error flag from read data according to whether an error is included in the read data outputted when a read operation is performed. The write operation control circuit generates a write control signal for controlling a write operation based on the error flag.

Semiconductor devices

A semiconductor device includes a flag generation circuit and a write operation circuit. The flag generation circuit generates an error scrub flag if an error scrub operation is performed. The write operation circuit controls a write operation in response to the error scrub flag. The error scrub operation includes an internal read operation for outputting read data from a cell array, a data correction operation for correcting an error included in the read data to generate corrected data, and an internal write operation for storing the corrected data into the cell array.

Methods of scrubbing errors and semiconductor modules using the same

A semiconductor device includes a read data generation circuit and a syndrome generation circuit. The read data generation circuit generates first read data from first output data and a first output parity which are generated during a first read operation. In addition, the read data generation circuit generates second read data from second output data and a second output parity which are generated during a second read operation. The syndrome generation circuit generates a syndrome signal from the first read data and the second read data. The syndrome generation circuit generates the syndrome signal so that column vectors of a first half matrix corresponding to the first read data are symmetric to column vectors of a second half matrix corresponding to the second read data.

Error correction methods and semiconductor devices using the same

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device generates a first error scrub control signal and a second error scrub control signal according to a logic level combination of an error code including information on the error occurrence number of times. The second semiconductor device performs an error scrub operation of a memory area on a first cycle time in response to the first error scrub control signal during a refresh operation and performs the error scrub operation of the memory area on a second cycle time in response to the second error scrub control signal during the refresh operation.

Semiconductor devices and semiconductor systems including the same

A semiconductor device includes an error count signal generation circuit and a row error control circuit. The error count signal generation circuit generates an error count signal which is enabled if the number of erroneous data of cells selected to perform an error scrub operation is equal to a predetermined number. The row error control circuit stores information concerning the number of the erroneous data in response to the error count signal if the number of the erroneous data is greater than or equal to the predetermined number or stores information concerning the number of row paths exhibiting the erroneous data in response to the error count signal after more erroneous data than the predetermined number is detected.

Semiconductor devices executing an error scrub operation

A semiconductor device may be provided. The semiconductor device may include an input and output (I/O) circuit configured to output transfer data generated from input data as internal data based on a write enablement signal and configured to output error information on the input data based on the write enablement signal. The generation of the write enablement signal may be based on a write signal which may be delayed by a delay time according to whether an error correction operation is performed.

Semiconductor device

A semiconductor device includes a write read control circuit for outputting a write enable signal which is enabled in response to a write command, and a test mode signal; and an error correction circuit suitable for performing a calculation operation of determining an error information of input data in response to the write enable signal and then outputting an internal parity signal including the error information, and outputting internal data by delaying the input data in response to the write enable signal.

A semiconductor device includes a delay selection signal generation circuit, an internal read signal generation circuit, and an internal write signal generation circuit. The delay selection signal generation circuit generates a delay selection signal in response to an information code signal. The internal read signal generation circuit generates an internal read signal from a mask write signal in response to the delay selection signal and a clock. The internal write signal generation circuit delays the mask write signal by a predetermined delay period to generate an internal write signal.

An integrated circuit includes a first semiconductor device suitable for outputting a first error information signal by performing a first error correction operation, and a second semiconductor device suitable for outputting a second error information signal by performing a second error correction operation. The first error correction operation and the second error correction operation are performed simultaneously, and the second error information signal is outputted from the second semiconductor device after the first error information signal is outputted from the first semiconductor device.

Integrated circuit

A semiconductor system may be provided. The semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to perform an error correction operation. The second semiconductor device may be configured to perform an error correction operation. The semiconductor system may selectively operate the first or second semiconductor devices with regards to error correction operations based on a mode signal.

Semiconductor devices and semiconductor systems

A semiconductor device includes a control signal generation circuit and an input/output (I/O) control circuit. The control signal generation circuit generates first and second read control signals and first and second write control signals. One of the first and second read control signals and one of the first and second write control signals is selectively enabled according to a combination of first and second addresses for selecting a first I/O line or a second I/O line. The I/O control circuit outputs read data loaded on first and second internal I/O lines through any one of the first and second I/O lines in response to the first and second read control signals. In addition, the I/O control circuit outputs input data through any one of the first and second I/O lines in response to the first and second write control signals.

A semiconductor apparatus includes a comparison voltage generation unit configured to generate a plurality of different comparison voltages, a reference voltage generation unit configured to receive a generation code from an external system, select one of the plurality of the different comparison voltages according to the generation code, and generate a reference voltage, and a reference voltage determination unit configured to receive the generation code and an expected reference voltage from the external system, check whether a level of the expected reference voltage is in a target range, and output a check result to the external system.

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Hwaseong-si, South Korea

Yong Mi Kim