Fairchild Semiconductor Corporation

Fairchild Semiconductor Corporatio

Yong Liu

Qiuxiao Qian

Tiburcio A Maldo

Hua Yang

Yumin Liu

Zhongfa Yuan

Margie T Rios

Stephen Martin

Howard Allen

Qi Wang

Jonathan A Noquil

Dan Kinzer

JiangYuan Zhang

Mike Speed

JungTae Lee

Scott Irving

Jiangyuan Zhang

Luke G England

Jocel P Gomez

William Robert Newberry

Timwah Luk

Honorio T Granada, Jr

Douglas Alan Hawks

Zhengyu Zhu

Jianhong Ju

Roger Luo

Luke Huiyong Chung

Huiyong Luke Chung

Jocel Gomezl

Jeff Ju

A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe.

Semiconductor die package including IC driver and bridge

A package is disclosed. The package includes a premolded substrate having a leadframe structure, a first device attached to the leadframe structure, and a molding material covering at least part of the leadframe structure and the first device. It also includes a second device attached to the premolded substrate.

Die package including substrate with molded device

A multiple die package includes a folded leadframe for interconnecting at least two die attached to another leadframe. In a synchronous voltage regulator the folded leadframe, which is formed from a single piece of material, connects the high side switching device with the low side switching device to provide a low resistance, low inductance connection between the two devices.

Folded leadframe multiple die package

A two tier power module has, in one form thereof, a PC board having upper and lower traces with an opening in the insulating material that contains a power device which has upward extending solder bump connections. An upper leadframe is mounted on the solder bumps and the upper tracks of the PC board. Vias in the PC board connect selected upper and lower traces. A control device is mounted atop the leadframe and wire bonded to the leadframe, and the assembly is encapsulated leaving exposed the bottom surfaces of the lower traces of the PC board as external connections. In another form the PC board is replaced by a planar leadframe and the upper leadframe has stepped sections which make connections with the planar leadframe, the bottom surfaces of the planar leadframe forming external connections of the module.

Semiconductor package with an embedded printed circuit board and stacked die

Disclosed are semiconductor die packages constructed from modules of embedded semiconductor dice and electrical components. In one embodiment, a semiconductor die package comprises a first module and a second module attached to the first module. One or more semiconductor dice are embedded in the first module, and one or more electrical components, such as surface-mounted components, are embedded in the second module. The first module may be formed by a lamination process, and the second module may be formed by a lamination process or a molding process. Patterned metal layers and vias provide electrical interconnections to the package and among the die and components of the package. The second module may be attached to the first module by coupling interconnect lands of separately manufactured modules to one another, or may be directly attached by lamination or molding.

Embedded semiconductor power modules and packages

This document discusses, among other things, a conductive frame, a silicon die coupled to the conductive frame, the silicon die including a vibratory diaphragm, the die having a silicon die top opposite a silicon die bottom, with a silicon die port extending through the silicon die to the vibratory diaphragm, with a silicon die terminal in electrical communication with the conductive frame and an insulator affixed to the conductive frame and the silicon die, with the insulator extending through interstices in the conductive frame to a conductive frame bottom of the conductive frame, and around an exterior of the silicon die to the silicon die top, with the insulator physically affixed to the silicon die and to the conductive frame, with the silicon die port exposed and with a conductive frame terminal disposed at the conductive frame bottom in electrical communication with the silicon die terminal.

Microelectromechanical systems microphone packaging systems

Optocoupler devices and methods for making and using such devices are described. The optocoupler devices contain a light emitting component (a light emitting diode [LED]) and a light receiving component (a phototransistor [PT]) device that are embedded within the substrate, rather than being attached to the surface of the pre-molded substrate. Such a configuration eliminates the bond wires that are often used when the LED and PT are attached on the substrate, improves the electrical performance, and allows the final optocoupler package to be made smaller and thinner. Other embodiments are described.

Optocoupler devices

A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with the exposed surfaces of the semiconductor dice proximate to each other.

Embedded die package on package (POP) with pre-molded leadframe

A molded, leadless packaged semiconductor multichip module includeshas four mosfetsfor a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In modulethere are two leadframesfor assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound. The resulting package has four upper heat sinks-that are exposed in the molding compoundfor transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDS. The top or source-drain lead framemay be soldered to the sources and gates of the bridge mosfets.

Four MOSFET full bridge module

Disclosed are semiconductor die packages, systems, and methods therefor. An exemplary package comprises a patterned conductive layer having a first surface, a second surface, and a first thickness between its first and second surfaces; a semiconductor die disposed over the first surface of the patterned conductive layer and electrically coupled thereto; a plurality of conductive bodies disposed at the second surface of the patterned conductive layer and electrically coupled thereto, each conductive body having a thickness that is greater than the first thickness; and a body of electrically insulating material disposed on the semiconductor die and a portion of the first surface of the patterned conductive layer. A further embodiment farther comprises a second semiconductor die disposed over the second surface of the patterned conductive layer and electrically coupled thereto.

Flexible and stackable semiconductor die packages having thin patterned conductive layers

Wafer level embedded and stacked die power system-in-package semiconductor devices, and methods for making and using the same, are described. The methods include placing a first side of a substrate frame, which includes through cavity and an adjacent via, on a carrier. A first side of a component selected from an active device and a passive device can be placed on the carrier, within the cavity. A perimeter of the cavity can be attached to a perimeter of the component. Material at a second side of the substrate frame can be removed so the via extends from the frame's first side to the frame's second side. The substrate frame and component can then be removed from the carrier so that routing can be distributed between the first side of the frame and the first side of the component to electrically connect the component with the via. Other embodiments are described.

Wafer level embedded and stacked die power system-in-package packages

A buck converter module includes a high side (HS) die having source, drain, and gate bonding pads on a front side of the HS die, a low side (LS) die having a first section thereof with a plurality of through silicon vias (TSVs) extending from a back side to a front side of the LS die, the LS die having source, drain, and gate bonding pads located on a front side of a second section separate from the first section, the drain bonding pad electrically connected to the back side of the LS die in the second section. The HS die and the LS die are bonded together such that the source bonding pad of the HS die is electrically connected to the back side of the LS die, and each of the drain and gate bonding pads are electrically connected to separate TSVs in the LS die.

Wafer level buck converter

This document discusses, among other things, apparatus and methods for an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components.

Wafer level stack die package

Disclosed are molded ultra-thin semiconductor die packages, systems that incorporate such packages, and methods of making such packages. An exemplary package comprises a leadframe having an aperture formed between the leadframe's first and second surfaces, and a plurality of leads disposed adjacent to the aperture. The package further comprises a semiconductor disposed in the aperture of the leadframe with its top surface substantially flush with the leadframe's first surface, and at least one gap between at least one side surface of the semiconductor die and at least one lead of the leadframe. A body of electrically insulating material is disposed in the at least one gap. A plurality of conductive members interconnect leads of the leadframe with conductive regions on the die's top surface, with at least one conductive member having a portion disposed over at least a portion of the body of insulating material.

Growing community of inventors

Scarborough, ME, United States of America

Yong Liu