International Business Machines Corporation

Globalfoundries Inc.

Yong Liu

Daniel Joseph Friedman

Jose A Tierno

Bipin Rajendran

Dharmendra S Modha

Leland Chang

Robert K Montoye

Steven Kyle Esser

Jae-sun Seo

Bernard V Brezzo

John Francis Bulzacchelli

Sergey Vladimirovich Rylov

Thomas Helmut Toifl

Pier Andrea Francese

Troy James Beukema

Seongwon Kim

Mihai A Sanduleanu

Zeynep Toprak Deniz

Joel Abraham Silberman

Phillip John Restle

Wing Kin Luk

Xiaoxiong Gu

Liang-Teck Pang

Timothy O Dickson

Woogeun Rhee

Xiaomin Duan

A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

Reconfigurable and customizable general-purpose circuits for neural networks

An analog-to-digital converter includes a plurality of slave sampler multiplexers responsive to outputs of a master sampler that receives analog signals and whose output ports connect to integrating threshold comparators having capacitive digital-to-analog conversion offset adjustments for forming an analog-to-thermometer code conversion. A calibration state machine receives outputs of each of the integrating threshold comparators to control the capacitive digital-to-analog conversion offset adjustment of every integrating threshold comparator and to control a calibration digital-to analog converter. A thermometer code to binary code logic decoder receives outputs of each of the integrating threshold comparators and outputs digital samples.

Analog to digital converter with high precision offset calibrated integrating comparators

A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.

Continuous-time linear equalizer for high-speed receiving unit

A receiver is adapted to receive an input signal having a first voltage swing and to generate an output signal having a second voltage swing, the output signal being indicative of the input signal, the second voltage swing being greater than the first voltage swing. The receiver includes a first sub-rate receiver block and at least a second sub-rate receiver block. A receiver clock is divided into a first sub-rate clock phase and at least a second sub-rate clock phase, the first sub-rate clock phase being used to drive the first sub-rate receiver block and the second sub-rate clock phase being used to drive the second sub-rate receiver block. Each of the first sub-rate receiver block and the second sub-rate receiver block includes at least one gated-diode sense amplifier.

Sub-rate low-swing data receiver

There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution circuit includes, on each of the two or more strata, phase detectors, a logic circuit, and a phase de-skewing element. Each phase detector has a respective output for providing phase information relating to a phase difference between two of the global clocks signals on respective different ones of the two or more strata. The logic circuit is connected to the respective outputs of the phase detectors for determining a phase adjustment plan for a given one of the two or more strata upon which the logic circuit is located responsive to the phase information. The phase de-skewing element is for adjusting a clock skew of a same stratum located one of the two of the global clock signals responsive to the phase adjustment plan.

Distributed phase detection for clock synchronization in multi-layer 3D stacks

A method and system are disclosed for calibrating a mid-voltage node in an integrated circuit including an input-output circuit having charge-recycling stacked voltage domains including at least first and second voltage domains. In one embodiment, the method comprises transmitting data through the input-output circuit, including transmitting a first portion of the data across the first voltage domain, and transmitting a second portion of the data across the second voltage domain. The method further comprises measuring a specified characteristic of the data transmitted through the input-output circuit; and based on the measured specified characteristic, adjusting a voltage of said mid-voltage node to a defined value. The voltage of the mid-voltage node may be adjusted to accomplish a number of objectives, for example, to achieve a desired trade-off between power and performance, or so that the two voltage domains have the same performance.

Calibration schemes for charge-recycling stacked voltage domains

A deserializer includes an input interface configured to receive an N-bit serialized stream at a source clock frequency; a modified-tree deserializing architecture that receives the first N&#x2212;1 bits of the serialized stream from the input interface and generates N&#x2212;1 parallel outputs corresponding to the first N&#x2212;1 bits; and a last-bit flip-flop that directly samples the input interface to obtain an Nth bit, such that all N bits are available within one source clock cycle after the Nth bit arrives at the input interface.

Low latency data deserializer

A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.

Compact low-power asynchronous resistor-based memory read operation and circuit

Circuits for shielding devices from electromagnetic coupling with through-silicon vias are shown that include a substrate having a through via, which provides access to a device layer on a first surface of the circuit to a device layer on a second surface of the circuit; a conductive layer on the first side of the substrate; a contact point on one of the device layers; and a grounded buried interface tie on the conductive layer, adjacent to the contact point, to isolate the contact point from coupling noise.

Through silicon via noise suppression using buried interface contacts

Growing community of inventors

Rye, NY, United States of America

Yong Liu