Samsung Electronics Co., Ltd.

Other

Yong Kyun Lim

Kyoung Min Koh

Han Vit Yang

Kyung-min Kim

Kyoung-Min Koh

Yu-Jin Park

Seog Heon Ham

Yu Jin Park

Jae Jin Jung

Soo Youn Kim

Chi Ho Hwang

Jin Woo Kim

Shin Hyoung Kim

Jin Ho Seo

Seung Jin Lee

Seog-Heon Ham

Seung Hyun Lim

Kwi Sung Yoo

Jaehoon Lee

Kwang-Hyun Lee

Seunghyun Oh

Seung-hyun Lim

Kwi-Sung Yoo

Moo Sup Lim

Jae Cheol Yun

Kyo-Jin Choo

Sung Ho Suh

Jae Geon Kim

Kee Moon Chun

Min Jin Han

Ju Ha Kim

Chi-Ho Hwang

Cheol Won Jang

An analog-to-digital converter of successive approximation register (SAR) type includes a comparator, a SAR logic circuit, and a capacitor digital-to-analog converter. The capacitor digital-to-analog converter includes a plurality of drivers. Each driver includes a capacitor and a split inverter. A first capacitor node of the capacitor is connected to one of comparison input terminals. The split inverter includes a pull-up unit connected to a first reference voltage and a pull-down unit connected to a second reference voltage. The split inverter drives a second capacitor node of the capacitor by selectively turning on one of the pull-up unit and the pull-down unit. A first one of the pull-up unit and the pull-down unit includes a full transistor, and a second one of the pull-up unit and the pull-down unit includes a first split transistor and a second split transistor. A short current is reduced using the split inverter.

Split inverter, capacitor digital-to-analog converter and analog-to-digital converter of successive approximation register type including same

A temperature controller for semiconductor fabrication comprises a lower chiller connected with a lower chamber of a processing chamber and configured to adjust a temperature of the lower chamber, an electrostatic chuck disposed in the lower chamber and an upper chiller connected with an upper chamber of the processing chamber and configured to adjust a temperature of the upper chamber, a heater disposed in the upper chamber. In the temperature controller for semiconductor fabrication, the three-way valve may be installed on the cooling fluid supplying pipe, and the bypass pipe may be installed between the three-way valve and the cooling fluid collecting pipe to reduce the degree of bypass opening of the three-way valve.

Temperature controller for manufacturing semiconductor

An image sensor includes a first column pair and a second column pair among a plurality of columns of a pixel array, an analog-to-digital converter pair, and a switch arrangement circuit configured to connect the first column pair with the analog-to-digital converter pair in response to first switch control signals such that two rows among a plurality of rows in the pixel array are read during a single access time.

Image sensor and system including the same

An image sensor includes a pixel array including at least one active pixel and at least one line-optical black (L-OB) pixel arranged in a matrix including first to nrows and first to mcolumns, the pixel array configured to output a pixel signal and a dark-level offset signal in units of columns during a read-out operation in one of the first to nrows; a row driver configured to output a selection control signal to the first to nrows; and an analog-to-digital converter (ADC) block configured to digitize the pixel signal and the dark-level offset signal. In the pixel array, a dark-level offset signal is simultaneously output from an L-OB pixel in another row during the read-out operation in one of the first to nrows. Here, 'n' and 'm' each denote an integer that is equal to or greater than &#x2018;2&#x2019;.

Image sensor

An image sensor may include a photodiode configured to convert an optical signal into photogenerated charge, a sensing node adjacent to the photodiode and configured to sense the photogenerated charge, a read-out circuit configured to convert the photogenerated charge into an electrical signal and to output the electrical signal through an output line, and/or at least one capacitor formed between the sensing node and a conversion gain control line. The conversion gain control line corresponding to the at least one capacitor may be selectively connected to a ground line or the output line based on at least one control signal.

Image sensors comprising photodiodes and image processing devices including the same

An analog-to-digital converter (ADC) within an image sensor includes a comparator comparing a ramp signal with an image signal, and a counter generating a count result in response to the comparison by counting a clock during a counting interval. The ADC determines whether a first counting interval for the counter is less than a reference interval, and if the first counting interval is less than the reference interval the counting interval is a first counting interval, else the counting interval is a second counting interval.

Analog-to-digital converter using variable counting interval and image sensor including same

An analog to digital converter (ADC) can include a multi-input comparison unit configured to compare a pixel voltage from an image sensor, a comparison voltage comprising a stepped voltage modified during a coarse mode of operation, and a ramp voltage comprising a ramped voltage modified to one another during a fine mode of operation, to provide a comparison result signal that indicates whether the comparison voltage combined with the ramp voltage is greater than or less than the pixel voltage. A selection control signal generation unit can receive the comparison result signal and a mode control signal, to indicate the coarse or fine mode, to provide a selection control signal allowing modification of the comparison voltage in the coarse mode and to hold the comparison voltage constant in the fine mode. A reference voltage selection unit can receive the selection control signal to control modification of the comparison voltage.

Analog to digital converters, image sensor systems, and methods of operating the same

A data transmission device includes a control unit and a delay chain unit. The control unit outputs a first control signal through an nth control signal, where n is a natural number. The delay chain unit includes a first switching element through an nth switching element. The switching elements receive a first data signal through an nth data signal and perform pipelining operations on the first through nth data signals based upon the first through nth control signals, respectively, to output the pipelined data signals as at least one data stream. The switching elements are connected to each other to form at least one data delay chain.

Data transmission device and image sensor system using the same

An image sensor includes a reference voltage generation unit that generates a reference voltage that alternately decreases and increases at a constant rate in an operation mode of the image sensor to convert analog signals of detected incident light to a digital value using the reference voltage to determine an intensity of the incident light with high sensitivity and high signal-to-noise ratio.

Image sensor and camera system having the same

A method of k*k subsampling, where k is an integer greater than one, a full frame readout on a plurality of pixels arranged in rows and columns, each pixel belonging to one of at least two sets, a first set configured to sense a first value of an image parameter and a second set configured to sense a second value of the image parameter, the method including sampling signals of k pixels of at least one set in a first row to output subsampled signals, converting the subsampled signals into digital signals having a lower resolution than the full frame readout, repeating sampling and converting for k rows, and adding digital signals for the first to kth rows within the at least one set.

Pseudo-digital average sub sampling method and apparatus

A dual-mode comparator may include an object voltage input unit that generates a first current flowing through a first path and a second current flowing through a second path based on a first object voltage and a second object voltage, a current mirror unit that performs a current-mirror operation for the first path and the second path to output a comparison voltage at an output terminal, a bias unit that generates a bias current corresponding to a sum of the first current and the second current, and a mode switching unit that controls the current mirror unit to have a first structure in an auto-zero mode and that controls the current mirror unit to have a second structure in a comparison mode.

Dual-mode comparator and analog to digital converter having the same

An analog-to-digital converter including a comparator configured to compare a pixel signal received at a first input terminal of the comparator with a ramp signal received at a second input terminal of the comparator and generate a comparison signal as a result of the comparison; and a ramp signal supply circuit configured to provide the ramp signal to the comparator, wherein the ramp signal supply circuit generates a first signal as part of the ramp signal in response to the comparison signal and a first clock signal being received at the ramp signal supply circuit, wherein a slope of the first signal sequentially changes until the comparison signal makes a transition from one logic level to another and, after the transition, the ramp signal supply circuit generates a second signal as part of the ramp signal, wherein a slope of the second signal sequentially changes, wherein the slope of the second signal is opposite the slope of the first signal.

Analog-to-digital converter and devices including the same

In one embodiment, the counter circuit is associated with a pixel array and includes a plurality of counting circuits. Each counting circuit is configured to receive an associated input signal, and each input signal is associated with a different column of the pixel array. A first of the plurality of counting circuits is configured to count based on the associated input signal. Each subsequent counting circuit in the plurality of counting circuits is configured to count based on a difference between the associated input signal and the input signal associated with a preceding counting circuit.

Counter circuit, analog-to-digital converter (ADC) including a counter circuit, image sensor including counter circuit and/or ADC, systems associated therewith, and method associated therewith

In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The counter includes at least one second stage for generating another bit of the value in the counter. An input clock signal is applied to a data input of the first stage and a clock input of the second stage.

Double data rate (DDR) counter, analog-to-digital converter (ADC) using the same, CMOS image sensor using the same and methods in DDR counter, ADC and CMOS image sensor

A method and apparatus subsampling a plurality of signals from one frame of a pixel array, pixels within the pixel array belonging to one of at least two sets, each set configured to sense values of a same image parameter, includes controlling integration times for first and second signals for each set output from the pixel array, controlling including using a first integration time for the first signal of the set and using a second integration time, different than the first integration time, for the second signal of the set, and calculating a synthesized value for each set using the first and second signals having different integration times.

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Suwon-si, South Korea

Yong Kyun Lim