Samsung Electronics Co., Ltd.

Yong-kyu Lee

Bo-young Seo

Jeong-Uk Han

Hee-Seog Jeon

Gwan-Hyeob Koh

Tea-Kwang Yu

Hong-kook Min

Dong-Gun Park

Young-Ho Kim

Dong-won Kim

Chang-Woo Oh

Byung-Gook Park

Sung-Taeg Kang

Jung-Ho Moon

Byung-yong Choi

Myung-Jo Chun

Choong-jae Lee

Jong-Duk Lee

Soung-Youb Ha

Yong-Tae Kim

Suk-Soo Pyo

Hyun-Khe Yoo

Ji-Hoon Park

Kee-Moon Chun

Dae-Shik Kim

Yong-Seok Chung

Byung-Sup Shim

Aliaksei Ivaniukovich

Choong-Jae Lee

Byung-Suo Shim

A semiconductor apparatus includes a substrate, a first insulating layer on a logic region and a memory region of the substrate, a second insulating layer on the first insulating layer, a base insulating layer between the first insulating layer and second insulating layer over the logic region and the memory region, first interconnection structures passing the first insulating layer, second interconnection structures passing through the second insulating layer, a base interconnection structure passing through the base insulating layer over the logic region, and a variable resistance structure in the base insulating layer over the memory region. The variable resistance structure includes a lower electrode, a magnetoresistive device, and an upper electrode, which are sequentially stacked. The lower electrode and the upper electrode are electrically connected to one of the first interconnection structures and one of the second interconnection structures, respectively, over the memory region.

Semiconductor apparatus including magnetoresistive device

A magnetic random-access memory (MRAM) device and a semiconductor package include a magnetic shielding layer that may suppress at least one of magnetic orientation errors and deterioration of magnetic tunnel junction (MTJ) structures due to external magnetic fields. A semiconductor device includes: a MRAM chip including a MRAM; and a magnetic shielding layer including an upper shielding layer and a via shielding layer. The upper shielding layer is on a top surface of the MRAM chip, and the via shielding layer extends from the upper shielding layer and passes through the MRAM chip.

Semiconductor devices and semiconductor packages including magnetic shielding layers and methods of manufacturing semiconductor devices and semiconductor packages

A resistive memory apparatus includes a memory cell array having a plurality of memory cells and a first ground switch. The plurality of memory cells are arranged in a plurality of rows and a plurality of columns, and each memory cell in a first column of the plurality of memory cells is connected between a first bitline and a first source line. The first ground switch is connected in parallel with the first source line, and the first ground switch is configured to selectively provide a first current path from the first bitline to ground through a selected memory cell in the first column of the plurality of memory cells and the first source line, the current path traversing only a portion of the first source line.

Memory apparatuses having ground switches

A semiconductor memory device includes a shorted variable resistor element in a memory cell. The semiconductor memory device includes main cells and reference cells each including a cell transistor and a variable resistor element. The variable resistor element of the reference cell is shorted by applying a breakdown voltage of a magnetic tunnel junction (MTJ) element, connection in parallel to a conductive via element, connection to a reference bit line at a node between the cell transistor and the variable resistor element, or replacement of the variable resistor element with the conductive via element. A sense amplifier increases a sensing margin of the main cell by detecting and amplifying a current flowing in a bit line of the main cell and a current flowing in the reference bit line to which a reference resistor is connected.

Semiconductor memory device including shorted variable resistor element of memory cell

A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution.

Semiconductor device including magneto-resistive device

A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.

Magnetic memory devices including magnetic memory cells having opposite magnetization directions

A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.

Magnetic memory devices including shared lines

Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well.

Semiconductor device having a diode

A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.

Non-volatile memory device

A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region.

Semiconductor device and method of fabricating semiconductor device

In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.

Electrically erasable programmable read-only memory (EEPROM) cell and methods for forming and reading the same

A non-volatile memory integrated circuit device and a method fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, word and select lines, and a floating junction region, a bit line junction region and a common source region. The semiconductor substrate has a plurality of substantially rectangular field regions, and the short and long sides of each substantially rectangular field region are parallel to the row and column directions of a matrix, respectively. The word lines and select lines extend parallel to the row direction on the semiconductor substrate, the word lines crossing a plurality of substantially rectangular field regions disposed in the row direction, and the select lines partially overlapping substantially rectangular field regions arranged in the row direction of the matrix, such that the parts of the long sides of the substantially field regions and the short sides of the substantially rectangular field regions are located below the select lines. The floating junction region is formed within the semiconductor substrate between the word lines and the select lines, the bit line junction region is formed opposite the floating junction region, and the common source region is formed opposite the floating junction region.

Growing community of inventors

Gwacheon-si, South Korea

Yong-kyu Lee