Lg Semicon Co., Ltd.

Yong Kwon Kim

Young Kwon Jun

Nae-Hak Park

Nae Hak Park

Chang Reol Kim

Jin-Won Park

A method of forming a metal line structure for use with a semiconductor device includes the steps of: preparing a semiconductor substrate; forming a first line on the semiconductor substrate; forming a plug pattern on the first line; forming at least one insulating layer on an exposed surface of the first line and on the plug pattern; planarizing the insulating layer and, simultaneously, removing the plug pattern to form a contact hole which exposes at least a portion of the first line; and forming a second line in the contact hole such that the second line is configured to couple with the first line.

Method for forming metal line

A method of forming an interconnection for a semiconductor device includes the steps of: forming a lower conductive line on a semiconductor substrate and forming a first insulating layer on the semiconductor substrate and the lower conductive line; patterning the first insulating layer to form a first insulating layer pattern which is narrower than the lower conductive line on the lower conductive line; forming a second insulating layer on an overall surface of the substrate and on the first insulating layer pattern, to planarize a surface of the second insulating layer; patterning the second insulating layer to expose a surface of the first insulating layer pattern and to form a first trench wider than the first insulating layer pattern on an upper portion of the first insulating pattern; removing the first insulating layer pattern, to thereby form a second trench at a lower portion of the first trench; and filling the first and second trenches with conductive material, to thereby form an upper conductive line.

Method for forming interconnection of semiconductor device

A method for fabricating wiring in a semiconductor device in which a conductor line and a contact hole are formed by self-alignment, includes the steps of: forming an insulating layer on a substrate; forming an etch-step layer on the insulating layer; etching the etch-stop layer of a wiring region connected to a window and the insulating layer to a predetermined thickness; forming a mask layer on the etch-stop layer and the insulating layer; etching the mask layer to remove the mask layer at the central part of the window; and etching the insulating layer of the central part of the window so as to form a contact hole. By applying such a method, a highly improved reliability can be obtained, and a process thereof is simplified by a single photolithography. Also, the contact hole is formed by self-alignment in the lengthwise direction and in the vertical direction of the conductor line.

Method for fabricating wiring in semiconductor device

A method for fabricating a charge coupled device (CCD) image sensor including the steps of: forming a plurality of photoelectric conversion regions and a plurality of vertical charge coupled device (VCCD) regions by a selective injection of second conductivity-type ions into a first conductivity-type semiconductor substrate; forming a plurality of transfer gate electrodes over the plurality of VCCD regions for transmitting image signal charges in four phases after forming a gate insulation film on the entire surface; depositing a first insulation film on the entire surface, and forming light shielding metal thereon; forming a first metal layer by selective removal of the optical shielding metal over the plurality of photoelectric conversion regions and the plurality of VCCD regions; forming contact holes for exposing the transfer gate electrodes the same clock signals applied thereto within one VCCD region of the plurality of VCCD regions, after depositing a second insulation film on the entire surface; and forming a second metal layer by depositing optical shielding and conductive metal on the entire surface, and carrying out patterning leaving the metal only on the plurality of the VCCD regions.

Growing community of inventors

Chungcheongbuk-do, South Korea

Yong Kwon Kim